Altera JNEye Instrukcja Użytkownika Pobierz pdf (Strona 173)

Figure 3-22: Phase Noise of Reference Clock and Its Transitions through PLL and CDR

At the output of the PCI-Express 8G receiver’s 1-Tap DFE, the following figures show that the DFE has

further opened the eye diagram with a total jitter of 1 UI (at BER < 10

-12

, with ideal clock and sinusoidal

jitter from the transmitter reference clock) and 0.53 UI (with CDR recovered clock) and eye diagram

opening height of 0 mV (with ideal clock) and 66 mV (with recovered clock). The BER bathtub curve and

contour show good behavior and successfully meet the PCI-Express 8GT RX requirements (TJ < 0.7 UI

and eye diagram height > 25 mV; refer to PCI-Express Base Specification 4.3).

3-22

Analysis

UG-1146

2015.05.04

Altera Corporation

Tutorial: PCI Express 8GT

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Altera JNEye Instrukcja Użytkownika Strona 173