Altera Mentor Verification IP Altera Edition AMBA AXI4-St Instrukcja Użytkownika Pobierz pdf (Strona 75)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3

April 2014

Chapter 7

VHDL API Overview

This section describes the VHDL API procedures for the BFM (master, slave, and monitor)

components. For each BFM, you can configure protocol transaction fields that execute on the

protocol signals and control the operational transaction fields that permit delays between the

handshake signals.

In addition, each BFM API has procedures that wait for certain events to occur on the system

clock and reset signals, and procedures to “get" and “set" information about a particular

transaction.

Note

The VHDL API is built on the SystemVerilog API. An internal VHDL to SystemVerilog

(SV) wrapper casts the VHDL BFM API procedure calls to the SystemVerilog BFM API

tasks and functions.

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Altera Mentor Verification IP Altera Edition AMBA AXI4-St Instrukcja Użytkownika Strona 75