Altera 100G Development Kit, Stratix V GX Edition Instrukcja Użytkownika Pobierz pdf (Strona 19)

Chapter 2: Board Components 2–11

MAX II CPLD EPM2210 System Controller

August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition

Reference Manual

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX

II CPLD, for the

following purposes:

■ FPGA configuration from flash memory

■ Power consumption monitoring

■ Temperature monitoring

■ Virtual JTAG interface for PC-based power and temperature GUI

■ Control registers for clocks

■ Control registers for Remote System Update

■ Control registers for general purpose I/O and PFL

■ Register with CPLD design revision and board information (read-only)

LCD_WEN 2.5-V LVCMOS output 1 LCD write enable

Ethernet

ENET_TXD[3:0] 2.5-V LVCMOS output 4 Ethernet transmit RGMII data bus

ENET_TX_EN 2.5-V LVCMOS output 1 Ethernet transmit enable

ENET_GTX_CLK 2.5-V LVCMOS output 1 Ethernet transmit clock

ENET_RXD[3:0] 2.5-V LVCMOS input 4 Ethernet receive RGMII data bus

ENET_RX_DV 2.5-V LVCMOS input 1 Ethernet receive data valid

ENET_RX_CLK 2.5-V LVCMOS input 1 Ethernet receive clock

ENET_INTN 2.5-V LVCMOS input 1 Ethernet management bus interrupt

ENET_MDC 2.5-V LVCMOS output 1 Ethernet RGMII clock

ENET_MDIO 2.5-V LVCMOS bidirectional 1 Ethernet RGMII data

ENET_RESETN 2.5-V LVCMOS output 1 Ethernet reset

Total I/O:

1020

Table 2–4. Stratix V GX I/O Usage Summary (Part 6 of 6)

Function I/O Type I/O Count Description

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 75 76

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Altera 100G Development Kit, Stratix V GX Edition Instrukcja Użytkownika Strona 19