Altera Arria GX Development Board Instrukcja Użytkownika Pobierz pdf (Strona 20)

2–10 Reference Manual Altera Corporation

Arria GX Development Board October 2007

Configuration Schemes

2. Set SW2 and SW3 to add or remove either the HSMC expansion

connector or MAX II device from the JTAG chain.

Figure 2–5 shows the JTAG chain connections.

Figure 2–5. JTAG Chain Connections

Table 2–5 shows the JTAG chain signals.

f For more information about programming Altera devices, refer to the

Altera Configuration Handbook.

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Table 2–5. JTAG Chain I/O Signals Note (1)

Signal Name Description

JTAG_TCK JTAG clock (USB-Blaster output)

JTAG_TMS JTAG mode select (USB-Blaster output)

JTAG_TDO Data input (USB-Blaster output)

FPGA_TDO Data output (USB-Blaster input)

HSMA_TDO HSMC data output

MAXII_TDI MAX II data input

MAXII_TDO MAX II data output

FPGA_TDI Arria GX device data input

FPGA_TDO Arria GX data output (USB Blaster input)

Note to Ta b le 2 –5 :

(1) All signals are LVTTL.

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 41 42

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