Altera Cyclone III FPGA Starter Board Instrukcja Użytkownika Pobierz pdf (Strona 24)

2–16 Altera Corporation

Cyclone III FPGA Starter Board Reference Manual April 2012

Memory

ddr_cke R13 Output SSTL-2 44

ddr_cs_n V 1 Output SSTL-2 24

ddr_ras_n V16 Output SSTL-2 23

ddr_we_n U15 Output SSTL-2 21

ddr_clk U2 Bidirectional SSTL-2 45

ddr_clk_n V2 Bidirectional SSTL-2 46

ddr_a0 U1 Output SSTL-2 29

ddr_a1 U5 Output SSTL-2 30

ddr_a2 U7 Output SSTL-2 31

ddr_a3 U8 Output SSTL-2 32

ddr_a4 P8 Output SSTL-2 35

ddr_a5 P7 Output SSTL-2 36

ddr_a6 P6 Output SSTL-2 37

ddr_a7 T14 Output SSTL-2 38

ddr_a8 T13 Output SSTL-2 39

ddr_a9 V13 Output SSTL-2 40

ddr_a10 U17 Outp

ut SSTL-2 28

ddr_a11 V17 Output SSTL-2 41

ddr_a12 U16 Output SSTL-2 42

ddr_dq0 U4 Bidirectional SSTL-2 2

ddr_dq1 V4 Bidirectional SSTL-2 4

ddr_dq2 R8 Bidirectional SSTL-2 5

ddr_dq3 V5 Bidirectional SSTL-2 7

ddr_dq4 P9 Bidirectional SSTL-2 8

ddr_dq5 U6 Bidirectional SSTL-2 10

ddr_dq6 V6 Bidirectional SSTL-2 11

ddr_dq7 V7 Bidirectional SSTL-2 13

ddr_dq8 U13 Bidirectional SSTL-2 54

ddr_dq9 U12 Bidirectional SSTL-2 56

ddr_dq10 U11 Bidirectional SSTL-2 57

ddr_dq11 V 15 Bidirectional SSTL-2 59

ddr_dq12 U14 Bidirectional SSTL-2 60

ddr_dq13 R11 Bidirectional SSTL-2 62

ddr_dq14 P10 Bidirectional SSTL-2 63

Table 2–14. DDR SDRAM Pinout (Part 2 of 3) Note (1)

Signal Name FPGA Pin Direction Type U4 (DDR) Pin

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Brak uwag

Altera Cyclone III FPGA Starter Board Instrukcja Użytkownika Strona 24