Altera Cyclone III LS FPGA Instrukcja Użytkownika Pobierz pdf (Strona 22)

6–4 Chapter 6: Board Test System

Using the Board Test System

Cyclone III LS FPGA Development Kit User Guide © October 2009 Altera Corporation

The Configure Menu

Each test design tests different functionality and corresponds to one or more

application tabs. Use the Configure menu to select the design you want to use.

Figure 6–2 shows the Configure menu.

To configure the FPGA with a test system design, perform the following steps:

1. On the Configure menu, click the configu

re command that corresponds to the

functionality you wish to test.

2. In the dialog box that appears, click Configure to download the corresponding

design’s SRAM Object File (.sof) to the FPGA. The download process usually takes

about a minute.

3. When configuration finishes, click Close to complete the configuration process

and run the design in the FPGA. A corresponding application tab appears in the

GUI that interfaces with the design in the FPGA.

The Config Tab

The Config tab shows information about the board’s current configuration.

Figure 6–1 on page 6–2 shows the Config tab.

The tab displays the contents of the

MAX II registers, the MAX II code version, the JTAG chain, the board’s MAC address,

and the

flash memory map.

The following sections describe the controls on the Co

nfig tab.

MAX-II Registers

These controls allow you to view and change the current MAX II register values as

described in Table 6–1. Changes to the register values with the GUI take effect

immediately. For example, selecting a new frequency in the OCR1 li

st immediately

changes the clock frequency on the board.

Figure 6–2. The Configure Menu

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 41 42

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