Altera Cyclone IV GX FPGA Development Board Instrukcja Użytkownika Strona 21

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Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
May 2013 Altera Corporation Cyclone IV GX FPGA Development Board
Reference Manual
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain. Figure 2–4 illustrates the JTAG chain.
The Cyclone IV GX FPGA is configured via JTAG using the MAX II configuration
controller design (embedded blaster) as the primary configuration mode. The board
includes a MAX II CPLD EPM2210 System Controller which interfaces directly to the
Cyclone IV GX FPGA for configuration, LCD control, power monitor control, and
other purposes. The MAX II CPLD EPM2210 System Controller contains the required
state machine and control logic to determine the configuration source for the Cyclone
IV GX FPGA.
Figure 2–4. JTAG Chain
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