Altera Cyclone V GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 35)

Chapter 2: Board Components 2–27

Components and Interfaces

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

HSMC

The development board supports a HSMC interface. This physical interface provides

four channels of 3.125 Gbps-capable transceivers. The HSMC interface also supports a

full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as

JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards

(HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

ENET_MDIO

D18 2.5-V CMOS Management bus data

ENET_RESETN

J17 2.5-V CMOS Device reset

ENET_RX_CLK

G17 2.5-V CMOS RGMII receive clock

ENET_RX_D0

AF8 2.5-V CMOS RGMII receive data bus

ENET_RX_D1

AB9 2.5-V CMOS RGMII receive data bus

ENET_RX_D2

AA9 2.5-V CMOS RGMII receive data bus

ENET_RX_D3

AH7 2.5-V CMOS RGMII receive data bus

ENET_RX_DV

D19 2.5-V CMOS RGMII receive data valid

ENET_TX_D0

AG7 2.5-V CMOS RGMII transmit data bus

ENET_TX_D1

AB8 2.5-V CMOS RGMII transmit data bus

ENET_TX_D2

AA8 2.5-V CMOS RGMII transmit data bus

ENET_TX_D3

AG8 2.5-V CMOS RGMII transmit data bus

ENET_TX_EN

K20 2.5-V CMOS RGMII transmit enable

ENET_XTAL_25MHZ

— 2.5-V CMOS 25-MHz RGMII transmit clock

MDI_P0