Altera Nios Development Board Instrukcja Użytkownika Pobierz pdf (Strona 14)

1–6 Altera Corporation

Nios Development Board Reference Manual, Stratix Edition September 2004

CompactFlash Connector

■ Pin 13 of CON3 (VCC) is driven by a power MOSFET that is

controlled by an FPGA I/O pin. This allows the FPGA to control

power to the CompactFlash card for the IDE connection mode.

■ Pin 26 of CON3 (-CD1) is pulled up to 5V through a 10 Kohm resistor.

This signal is used to detect the presence of a CompactFlash card;

when the card is not present, the signal is pulled high through the

pull-up resistor.

■ Pin 41 of CON3 (RESET) is pulled up to 5V through a 10 Kohm

resistor, and is controlled by the EPM7128AE configuration

controller. The FPGA can cause the configuration controller to assert

RESET, but the FPGA does not drive this signal directly.

1 The CompactFlash connector shares several Stratix I/O pins

with expansion prototype connector PROTO1. See 2“Expansion

Prototype Connector (PROTO1)” on page 1–11 for details on

PROTO1.

Table 1–2 below provides CompactFlash pin out details.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 51 52

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