Altera Nios II C2H Compiler Instrukcja Użytkownika Strona 15
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Altera Corporation 9.1 1–9
November 2009 Nios II C2H Compiler User Guide
Introduction to the C2H Compiler
System Architecture
Figure 1–1 shows the architecture of a simple Nios II processor system
that includes one hardware accelerator.
Figure 1–1. Example System Topology with Single Hardware Accelerator
SOPC Builder automatically integrates the accelerator logic into the
system as an SOPC Builder component. If there is more than one
accelerator in the system, multiple accelerators appear in SOPC Builder.
Accelerators are separate from the Nios II processor but can access the
same memory devices that the Nios II processor can.
Nios II
Processor
M
Hardware
Accelerator
Data
Memory
S
Arbitrator
Peripherals
S
S
Instruction
M
Data
MM
Control
Arbitrator
S
Instruction
Memory
Avalon
Switch
Fabric
Write Data & Control Path
Read Data
M
S
Avalon Master Port
Avalon Slave Port
MUX
Data
Memory
S
- Nios II C2H Compiler 1
- User Guide 1
- UG-N2C2HCMPLR-1.6 2
- Contents 3
- Chapter 6. Pragma Reference 4
- 1. Introduction to the 7
- Target Audience 8
- Introduction 8
- Altera Corporation 9.1 1–5 11
- C2H Compiler 12
- Concepts 12
- Hardware and Software 13
- 1–8 9.1 Altera Corporation 14
- C2H Compiler Concepts 14
- System Architecture 15
- Appropriate for 19
- Hardware 19
- Acceleration 19
- Poor Acceleration Candidates 20
- Next Steps 22
- 2. Getting Started Tutorial 23
- Typical Design 24
- OpenCore Plus Evaluation 25
- Tutorial 26
- Altera Corporation 9.1 2–5 27
- Getting Started Tutorial 27
- Create the Software Project 28
- Altera Corporation 9.1 2–7 29
- 2–8 9.1 Altera Corporation 30
- Altera Corporation 9.1 2–9 31
- Rebuild the Project 32
- Remove the Accelerator 37
- 3. C-to-Hardware Mapping 41
- Reference 41
- Assignments 42
- >> 44
- << 44
- Iteration Statements 45
- Selection Statements 46
- Altera Corporation 9.1 3–7 47
- Conditional Operator ?: 48
- Altera Corporation 9.1 3–9 49
- Subfunction Calls 51
- Variable 53
- Declarations 53
- Scalar Variables 54
- Accesses 55
- Memory Accesses 58
- Volatile Type Qualifier 59
- Address Computation 61
- Data Computation 62
- Master-Slave Connections 63
- Array Subscript Operator 66
- Structure and Union Operators 68
- Scheduling 70
- Data Dependencies 71
- Pointer Aliasing 72
- int offset_b) 75
- my_ptr[offset_a] = a + 7; 75
- my_ptrb[offset_b] = b + 8; 75
- Read Operations with Latency 77
- Stalling 79
- Loop Pipelining 82
- Loop-Carried Dependencies 84
- Subfunction Pipelining 89
- Resource 91
- Resource Sharing 92
- 4. Understanding the C2H 95
- Configuration Meaning 96
- Altera Corporation 9.1 4–5 99
- 4–6 9.1 Altera Corporation 100
- Resources 100
- Altera Corporation 9.1 4–7 101
- Understanding the C2H View 101
- 4–8 9.1 Altera Corporation 102
- Altera Corporation 9.1 4–9 103
- Performance 104
- Loop Latency 105
- Scheduling Information 108
- Further Reading 113
- 5. Accelerating Code Using 115
- Tools Command Line 115
- Altera Corporation 9.1 5–3 117
- 5–4 9.1 Altera Corporation 118
- C2H Performance Metrics 118
- 6. Pragma Reference 119
- Reducing Arbitration Logic 120
- Flow Control 121
- Interrupt 122
- Unshare Pointer 123
- 6–6 9.1 Altera Corporation 124
- Unshare Pointer Pragma 124
- 7. ANSI C Compliance and 125
- Restrictions 125
- 7–2 9.1 Altera Corporation 126
- Language 126
- Expressions 127
- Functions 128
- Altera Corporation 9.1 7–5 129
- 7–6 9.1 Altera Corporation 130
- Altera Corporation 9.1 7–7 131
- Goto (Section 6.8.6.1) 132
- Other Restrictions 134
- Additional Information 135
- Revision History 136
- How to Contact 137
- Typographic 137
- Conventions 137
- Visual Cue Meaning 138
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