Altera SDI Audio IP Cores Instrukcja Użytkownika

SDI Audio IP Cores User GuideLast updated for Altera Complete Design Suite: 14.0101 Innovation DriveSan Jose, CA 95134www.altera.comUG-SDI-AUD2014.06.

3SDI Audio IP Functional Description2014.06.30UG-SDI-AUDSubscribeSend FeedbackThe following sections describe the block diagrams and components for th

Figure 3-1: SDI Audio Embed IP Core Block DiagramAvalon-ST Audio to Audio Embed with Avalon OnlyFIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFOAudioEmbedderSD

Table 3-1: SDI Audio Embed ParametersDescriptionValueParameterSpecifies the maximum number of audio groups supported.Each audio group consists of 4 au

DescriptionValueParameterTurn on to include the Avalon-MM control interface.When you turn on this parameter, the register interface signalsappear at t

• A register interface block that provides support for an Avalon-MM control busThe clock recovery block recreates a 64 × sample rate clock, which you

DescriptionValueParameterTurn on to enable the logic to recover both a sample rate clock and a 64 ×sample rate clock.With HD-SDI inputs, the core gene

SDI Clocked Audio Output IP CoreThe SDI Clocked Audio Output IP core accepts clocked Avalon-ST audio and converts to audio in modifiedAES formats.SDI

Avalon-ST Audio InterfaceTo allow the standard components inside Qsys to interconnect, you must define the Avalon-ST audiointerface. The Avalon-ST aud

audio data size is configurable at compile time and matches the audio data sample size. Including the aux,the audio data word would be 24 bits.In Aval

This figure shows an example of two audio channels, where the channel signal indicates either channel 1 orchannel 2. Each channel has a start of packe

ContentsSDI Audio IP Overview...1-1SDI Audio IP Getting Started...

5. Click Finish.6. In the IP Catalog (Tools > IP Catalog), locate and double-click the variant audio_embed_avalon_top.vfile.The SDI Audio Embed par

4SDI Audio IP Interface Signals2014.06.30UG-SDI-AUDSubscribeSend FeedbackSDI Audio Embed SignalsThe following tables list the signals for the SDI Audi

Table 4-2: SDI Audio Embed Video Input and Output SignalsDescriptionDirectionWidthSignalThe video clock that is typically 27 MHz for SD-SDI, 74.25 MHz

This table lists the audio input signals.Table 4-3: SDI Audio Embed Audio Input SignalsN is the number of audio group.DescriptionDirectionWidthSignalS

Table 4-5: SDI Audio Embed Register Interface SignalsDescriptionDirectionWidthSignalClock for the Avalon-MM register interface.Input[0:0]reg_clkReset

DescriptionDirectionWidthSignalThis signal does the same function as the sine channel 4 frequencyregister.Input[7:0]sine_freq_ch4Channel status RAM ad

Table 4-8: SDI Audio Extract Video Input SignalsDescriptionDirectionWidthSignalThe video clock that is typically 27 MHz for SD-SDI, 74.25 MHzor 74.17

DescriptionDirectionWidthSignalSome audio receivers provide a word select output to align theserial outputs of several audio extract cores. In these c

Table 4-11: SDI Audio Extract Direct Control Interface SignalsDescriptionDirectionWidthSignalClock for the direct control interface.Input[0:0]reg_clkT

DescriptionDirectionWidthSignalAudio word select.Input[0:0]aes_wsAudio data input in internal AES format.Input[0:0]aes_dataThis table lists the Avalon

SDI Audio Embed Registers...5-1SDI

This table lists the input and output signals.Table 4-15: SDI Audio Clocked Output Input and Output SignalsDescriptionDirectionWidthSignalAudio input

DescriptionDirectionWidthSignalReset for the Avalon-MM register interface.Input[5:0]reg_base_addrTransfer size in bytes.Input[5:0]reg_burst_countWait

5SDI Audio IP Registers2014.06.30UG-SDI-AUDSubscribeSend FeedbackSDI Audio Embed RegistersThe following tables list the registers for the SDI Audio Em

Table 5-2: SDI Audio Embed RegistersDescriptionAccessNameBitAudio Control RegisterEnables the embedding of each audio group. When workingwith HD-SDI o

Video Status RegisterReports the detected video input standard.• Bits[7:5] = Picture structure code. Defined values forpicture structure code are:• 00

Strip Control RegisterEnables the removal of both ACP and ADP (and anySD-SDI EDP) for each of the four audio groups.RWStrip enable3:0Reserved for futu

Table 5-3: SDI Audio Extract Register MapNameBytes OffsetAudio Control Register00hAudio Presence Register01hAudio Status Register02hSD EDP Presence Re

Audio Presence RegisterWhen you specify the Channel Status RAM parameter to2, this field selects the channel pair for the RAM written toby registers 1

SD EDP Presence RegisterReports which audio extended data groups are detected inthe SD-SDI stream.ROEDP Present3:0Reserved for future use.—Unused7:4Er

Clock Status RegisterTo create a 48-kHz signal synchronous to the video clock,you must detect whether a 1 or 1/1.001 video clock rate isused. If you d

1SDI Audio IP Overview2014.06.30UG-SDI-AUDSubscribeSend FeedbackThe Altera®SDI Audio MegaCore®functions ease the development of video and image proces

SDI Clocked Audio Output RegistersThe following tables list the registers for the SDI Clocked Audio Output IP core.Table 5-7: SDI Clocked Audio Output

6SDI Audio IP Design Example2014.06.30UG-SDI-AUDSubscribeSend FeedbackAltera provides a design example with the SDI Audio Embed and Extract IP cores.

SDI Transmitter P0The triple-standard SDI transmitter that outputs a 3G-SDI (2.970 Gbps), HD-SDI (1.485 Mbps), or SD-SDI(270 Mbps) data stream. This t

Transceiver Dynamic Reconfiguration Control LogicThe transceiver dynamic reconfiguration control logic block handles the reconfiguration of the receiv

This table lists the function of each user-defined dual in-line package (DIP) switch settings.Table 6-2: Function of Each DIP SwitchDescriptionDIP Swi

Transmit SD-SDI with Embedding of Audio Group 1To transmit the SD-SDI video standard, follow these steps:1. Set DIP switch[2:1] = 002. The demonstrati

Figure 6-3: Condition of LEDs for Transmitting HDI-SDI Video StandardD6 D7 D8 D9 D10 D11 D12 D13D16 D17 D18 D19 D20 D21 D22 D233. The external wavefor

d. LED D17 illuminates when the receiver is frame locked.e. LED D18 illuminates when the receiver is TRS locked.f. LED D19 illuminates when the receiv

7Additional Information2014.06.30UG-SDI-AUDSubscribeSend FeedbackAdditional information about the document and Altera.Document Revision HistoryChanges

Related Information• www.altera.com/support• www.altera.com/training• www.altera.com/literatureAdditional InformationAltera CorporationSend FeedbackUG

Related Information• Serial Digital Interface (SDI) IP Core User GuideFor information about SDI IP core.• SDI II IP Core User GuideFor information abo

2SDI Audio IP Getting Started2014.06.30UG-SDI-AUDSubscribeSend FeedbackInstalling and Licensing IP CoresThe Quartus II software includes the Altera IP

• Program a device with your IP core and verify your design in hardwareOpenCore Plus evaluation supports the following two operation modes:• Untethere

Figure 2-2: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationThe IP Catalog and p

• Specify options for processing the IP core files in other EDA tools.4. Click Finish or Generate to generate synthesis and other optional files match