Altera Stratix IV GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 6)

1–2 Chapter 1: Overview

Board Component Blocks

Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation

■ EP4SGX530KH40 FPGA in the 1517-pin FineLine BGA Package

■ 531,200 LEs

■ 212,480 adaptive logic modules (ALMs)

■ 27,376 Kbit on-die memory

■ 24 transceivers (8.5 Gbps)

■ 2 PCI Express hard IP blocks

■ 8 phase locked loops (PLLs)

■ 1,024 18x18 multipliers

■ 0.9-V core power

■ MAX

II CPLD EPM2210 System Controller in the 256-pin FineLine BGA Package

■ 1.8-V core power

■ FPGA Configuration Circuitry

■ MAX

II CPLD EPM2210 System Controller and Flash Fast Passive Parallel

(FPP) configuration

■ On-Board USB-Blaster

for use with the Quartus

II Programmer

■ On-Board Clocking Circuitry

■ 50-MHz/125-MHz/155.52-MHz/156.25-MHz fixed-frequency oscillators

■ 100-MHz oscillator, programmable to any frequency between 20–810 MHz

■ 148.5-MHz voltage-controlled crystal oscillator (VCXO)

■ SMA connectors for external clock input

■ SMA connector for clock output

■ Memory devices

■ 512-Mbyte DDR3 SDRAM with a 64-bit data bus (bottom port)

■ 128-Mbyte DDR3 SDRAM with a 16-bit data bus (top port)

■ Two 4-Mbyte QDRII+ SRAMs with 18-bit data buses

■ 2-Mbyte SSRAM with 36-bit data bus

■ 64-Mbyte synchronous flash

■ General User I/O

■ 16 user LEDs

■ Two-line character LCD display

■ One configuration done LED

■ One transmit/receive LED (TX/RX) per HSMC interface

■ Four PCI Express LEDs

■ Four Ethernet LEDs

1 2 3 4 5 6 7 8 9 10 11 ... 77 78

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Altera Stratix IV GX FPGA Development Board Instrukcja Użytkownika Strona 6