Altera Stratix IV GX FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 30)

2–22 Chapter 2: Board Components

Clock Circuitry

Stratix IV GX FPGA Development Board August 2012 Altera Corporation

Reference Manual

Clock Circuitry

This section describes the board's clock inputs and outputs.

Stratix IV GX FPGA Clock Inputs

The development board has two types of clock inputs: global clock inputs and

transceiver reference clock inputs.

Figure 2–6 shows the Stratix IV GX FPGA development board global clock inputs. The

Stratix IV GX FPGA development board transceiver reference clock inputs are shown

in Figure 2–7.

Figure 2–6. Stratix IV GX FPGA Development Board Global Clock Inputs

B1B2

B6B5

CLK2p

CLK3p

CLKIN_50

HSMA_CLK_IN0

2.5V, NO OCT

REFCLK INPUT

SMA SMA

LVPECL or

Single-Ended

2-to-4 buffer

100 M*

CLK_SEL

CLKINRT_100_P

CLKINLT_100_P

CLKINTOP_100_P

CLKINBOT_100_P

DIPSW

SW4-5

To REFCLK

Clock Inputs

CLK1p

CLK0p

CLK9p

CLK8p

CLK10p

CLK11p

CLK7p

CLK6p

CLK4p

CLK5p

CLK13p

CLK12p

CLK14p

CLK15p

PLL

HSMA_CLK_IN_P2

LVDS, OCT 100 Ω

CLK_125_P

LVDS, Differential OCT

HSMB_CLK_IN0

2.5V, NO OCT

CLKINBOT_100_P

LVDS, Differential OCT

HSMA_CLK_IN_P1

LVDS, OCT 100 Ω

HSMB_CLK_IN_P1

LVDS, OCT 100 Ω

HSMB_CLK_IN_P2

LVDS, OCT 100 Ω

CLKINTOP_100_P

LVDS, Differential OCT

*The 100 MHz oscillator (X6) can be programmed

to any frequency between 10 MHz and 800 MHz

but powers up to 100 MHz using the clock control

GUI installed with the kit CD.

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