Altera Stratix GX Podręcznik Użytkownika

101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.comStratix GX Transceiver User GuideUG-STXGX-3.0P25-10021-02

1–2 Altera CorporationStratix GX Transceiver User Guide January 2005Transceiver Block ArchitectureTransceiver Block ArchitectureFigure 1–1 shows a

4–18 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode ClockingOne of the clocking interfaces to consider while designing

Altera Corporation 4–19January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–14. Example of a Multi-Transceiver Block FPGA to Transmitt

4–20 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode ClockingStratix GX logic array clock usage can be reduced by using

Altera Corporation 4–21January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–15. Inter-Transceiver Line Connections for EP1SGX25 Device

4–22 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode ClockingFigure 4–16 shows the transceiver routing with respect to I

Altera Corporation 4–23January 2005 Stratix GX Transceiver User GuideSONET ModeSONET Mode MegaWizard Plug-In ManagerThis section describes the alt

4–24 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode MegaWizard Plug-In ManagerFigure 4–17. MegaWizard Plug-In Manager -

Altera Corporation 4–25January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–18. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - Ge

4–26 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode MegaWizard Plug-In ManagerFigure 4–19. MegaWizard Plug-In Manager -

Altera Corporation 4–27January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–20. MegaWizard Plug-In Manager - ALTGXB (Page 6 of 9) - Re

Altera Corporation 1–3January 2005 Stratix GX Transceiver User GuideIntroductionTransmitter & Receiver PLLsEach gigabit transceiver block cont

4–28 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode MegaWizard Plug-In ManagerFigure 4–21. MegaWizard Plug-In Manager -

Altera Corporation 4–29January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–22. MegaWizard Plug-In Manager - ALTGXB (Page 8 of 9) - Tr

4–30 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode MegaWizard Plug-In ManagerFigure 4–23. MegaWizard Plug-In Manager -

Altera Corporation 5–1January 2005 5. XAUI ModeIntroductionThe 10 Gigabit Attachment Unit Interface (XAUI) is an optional, self-managed interfa

5–2 Altera CorporationStratix GX Transceiver User Guide January 2005IntroductionFigure 5–1. XGMII & XAUI Relationship to ISO/IEC Open Systems I

Altera Corporation 5–3January 2005 Stratix GX Transceiver User GuideXAUI ModeXAUI functions as a self-managed interface because code-group synchro

5–4 Altera CorporationStratix GX Transceiver User Guide January 2005IntroductionFigure 5–2. Example of Mapping XGMII Characters to PCS Code-GroupsT

Altera Corporation 5–5January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–3. Block Diagram of a Duplex Channel Configured in XAUI Mode

5–6 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver ArchitectureWord AlignerFor embedded clocking schemes, the c

Altera Corporation 5–7January 2005 Stratix GX Transceiver User GuideXAUI ModeThis module matches the 10-bit comma specified in the MegaWizard® Plu

1–4 Altera CorporationStratix GX Transceiver User Guide January 2005Transceiver Block ArchitectureTransmitter & Receiver Phase Compensation FIF

5–8 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver ArchitectureFigure 5–6. IEEE 802.3ae PCS Synchronization Sta

Altera Corporation 5–9January 2005 Stratix GX Transceiver User GuideXAUI ModeChannel AlignerYou use the channel aligner when implementing the XAUI

5–10 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver ArchitectureFigure 5–8. IEEE802.3ae PCS Deskew State Diagra

Altera Corporation 5–11January 2005 Stratix GX Transceiver User GuideXAUI ModeStratix GX transceivers handle XAUI channel alignment with a dedicat

5–12 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver Architecture10-Bit DecodingThe 8B/10B decoder translates th

Altera Corporation 5–13January 2005 Stratix GX Transceiver User GuideXAUI ModeDisparity Error DetectorThe 8B/10B decoder detects disparity errors

5–14 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver ArchitectureFigure 5–10. Disparity ErrorControl DetectThe 8

Altera Corporation 5–15January 2005 Stratix GX Transceiver User GuideXAUI ModePCS - XGMII Code ConversionIn XAUI mode, the 8b/10b decoder in Strat

5–16 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Receiver ArchitectureThe byte deserializer outputs up to 26 bits, de

Altera Corporation 5–17January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–13. Receiver Byte Deserializer in 8/16-Bit Mode With Alignm

Altera Corporation 1–5January 2005 Stratix GX Transceiver User GuideIntroductionChannel AlignerAn embedded channel aligner aligns byte boundaries

5–18 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Transmitter ArchitectureReceiver Phase Compensation FIFO ModuleThe r

Altera Corporation 5–19January 2005 Stratix GX Transceiver User GuideXAUI Modereceive a clock supply. In this case, there must be no frequency dif

5–20 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Transmitter ArchitectureXGMII Character to PCS Code-Group MappingIn

Altera Corporation 5–21January 2005 Stratix GX Transceiver User GuideXAUI ModeTable 5–4 lists the XGMII character-to -PCS code-group mapping.8B/10

5–22 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode Transmitter ArchitectureFigure 5–18. 8B/10B Conversion Format8B/10B

Altera Corporation 5–23January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–19. Transmitter Output During Reset ConditionsNote to Figur

5–24 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode ClockingAn example is the invalid encoding of a K24.1 (data = 8&apos

Altera Corporation 5–25January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–21. Default Configuration of altgxb Megafunction in XAUI Mo

5–26 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode ClockingFigure 5–22. Train Receiver PLL CRU Clock From Transmitter P

Altera Corporation 5–27January 2005 Stratix GX Transceiver User GuideXAUI ModeThe tx_coreclk must be frequency matched with its respective read po

1–6 Altera CorporationStratix GX Transceiver User Guide January 2005Modes of OperationFigure 1–2. Block Diagram of a Duplex Channel Configured in B

5–28 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode ClockingXAUI Inter-Transceiver Block ClockingThis section describes

Altera Corporation 5–29January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–24. PLD to Transmit Interface Clocking Scheme in a Multi-Ch

5–30 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode ClockingFigure 5–25. Clocking Scheme in Multi-Channel, Only CORECLK_

Altera Corporation 5–31January 2005 Stratix GX Transceiver User GuideXAUI ModeAnother multi-transceiver block issue is the selection of the dedica

5–32 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode ClockingFigure 5–26. IQ Line Connections for EP1SGX25 DeviceFigure 5

Altera Corporation 5–33January 2005 Stratix GX Transceiver User GuideXAUI ModeFor example, if a refclkb pin is required to feed a transmitter PLL

5–34 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode MegaWizard Plug-In ManagerXAUI Mode MegaWizard Plug-In ManagerThis s

Altera Corporation 5–35January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–28. MegaWizard Plug-In Manager - ALTGXB (Page 3 of 9) - Gen

5–36 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode MegaWizard Plug-In ManagerFigure 5–29. MegaWizard Plug-In Manager -

Altera Corporation 5–37January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–30. MegaWizard Plug-In Manager - ALTGXB (Page 5 of 9) - Rec

Altera Corporation 1–7January 2005 Stratix GX Transceiver User GuideIntroductionFigure 1–3. Block Diagram of a Duplex Channel Configured in SONET

5–38 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode MegaWizard Plug-In ManagerFigure 5–31. MegaWizard Plug-In Manager -

Altera Corporation 5–39January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–32. MegaWizard Plug-In Manager - ALTGXB (Page 7 of 9) - Rec

5–40 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode MegaWizard Plug-In ManagerFigure 5–33. MegaWizard Plug-In Manager -

Altera Corporation 5–41January 2005 Stratix GX Transceiver User GuideXAUI ModeFigure 5–34. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) - Sum

5–42 Altera CorporationStratix GX Transceiver User Guide January 2005XAUI Mode MegaWizard Plug-In Manager

Altera Corporation 6–1January 2005 6. GigE ModeIntroductionThe Gigabit Ethernet (GigE) mode in Stratix®GX devices supports a subset of the IEEE

6–2 Altera CorporationStratix GX Transceiver User Guide January 2005IntroductionFigure 6–1. GMII Position Relative to OSI Reference ModelStratix GX

Altera Corporation 6–3January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–2. Block Diagram of a Duplex Channel Configured in GigE Mode

6–4 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Receiver ArchitectureGigE Mode Receiver ArchitectureFigure 6–3 shows

Altera Corporation 6–5January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–4. Components in Stratix GX Word AlignerFor embedded clockin

1–8 Altera CorporationStratix GX Transceiver User Guide January 2005Modes of OperationFigure 1–4. Block Diagram of a Duplex Channel Configured in X

6–6 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Receiver ArchitectureIn GigE mode, the MegaWizard® Plug-In Manager de

Altera Corporation 6–7January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–6. Example of Completed SynchronizationThe receiver remains

6–8 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Receiver ArchitectureFigure 6–7. Synchronization Diagram State Machin

Altera Corporation 6–9January 2005 Stratix GX Transceiver User GuideGigE ModeRate MatcherThe GigE mode operates in multi-crystal environments, whi

6–10 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Receiver ArchitectureFigure 6–9. Idle Generation Without /I1/ Ordere

Altera Corporation 6–11January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–11. Addition of an /I2/ Ordered Set During an Almost Empty

6–12 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Receiver ArchitectureReset The rxdigitalreset signal governs the res

Altera Corporation 6–13January 2005 Stratix GX Transceiver User GuideGigE ModeAt time n + 4, because the current disparity is negative, a K28.5 fr

6–14 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Transmitter ArchitectureFigure 6–14. Control Code DetectionReceiver

Altera Corporation 6–15January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–15. Block Diagram of Transmitter Components Configured in G

Altera Corporation 1–9January 2005 Stratix GX Transceiver User GuideIntroductionFigure 1–5. Block Diagram of a Duplex Channel Configured in GigE M

6–16 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Transmitter ArchitectureThe transmitter phase compensation FIFO buff

Altera Corporation 6–17January 2005 Stratix GX Transceiver User GuideGigE Modethe same as the beginning running disparity (right before the idle c

6–18 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode Transmitter ArchitectureFigure 6–18. 8B/10B Conversion FormatResetAf

Altera Corporation 6–19January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–19. Even Number of /Dx.y/ Between Last Automatically Sent /

6–20 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingGigE Mode ClockingGigE Mode Channel Clocking This section de

Altera Corporation 6–21January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–21 shows the altgxb megafunction configured so that the tra

6–22 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingFigure 6–22. Receiver PLL CRU Clock From Transmitter PLL is

Altera Corporation 6–23January 2005 Stratix GX Transceiver User GuideGigE ModeYou can optionally enable the write clock of the transmitter phase c

6–24 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingFigure 6–23. TX_CORECLK & RX_CORECLK Enabled With RX_CRU

Altera Corporation 6–25January 2005 Stratix GX Transceiver User GuideGigE ModeGigE Mode Inter-Transceiver ClockingThis section provides guidelines

1–10 Altera CorporationStratix GX Transceiver User Guide January 2005Modes of Operation

6–26 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingFigure 6–24. Example of a Multi-Transceiver PLD to Transmitt

Altera Corporation 6–27January 2005 Stratix GX Transceiver User GuideGigE ModeWhen determining the location of REFCLKB pins, consider what can be

6–28 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingFigure 6–25. Inter-transceiver Line Connections for EP1SGX25

Altera Corporation 6–29January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–26 shows the transceiver routing with respect to inter-tran

6–30 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode ClockingFigure 6–26. Inter-transceiver Line Connections for EP1SGX40

Altera Corporation 6–31January 2005 Stratix GX Transceiver User GuideGigE ModeGigE Mode MegaWizardThis section describes the altgxb megafunction o

6–32 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode MegaWizardFigure 6–27. MegaWizard Plug-In Manager - ALTGXB (Page 3 o

Altera Corporation 6–33January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–28. MegaWizard Plug-In - ALTGXB (Page 4 of 9) - General (2)

6–34 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode MegaWizardFigure 6–29. MegaWizard Plug-In Manager - ALTGXB (Page 5 o

Altera Corporation 6–35January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–30. MegaWizard Plug-In Manager - ALTGXB (Page 6 of 9) - Rec

Altera Corporation 2–1January 2005 2. Stratix GX AnalogDescriptionIntroductionThis chapter describes how to serialize the parallel data for tra

6–36 Altera CorporationStratix GX Transceiver User Guide January 2005GigE Mode MegaWizardFigure 6–31. MegaWizard Plug-In Manager - ALTGXB (Page 7 o

Altera Corporation 6–37January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–32. MegaWizard Plug-In Manager - ALTGXB (Page 8 of 9) - Tra

6–38 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExampleFigure 6–33. MegaWizard Plug-In Manager - ALTGXB (Page 9 of 9) -

Altera Corporation 6–39January 2005 Stratix GX Transceiver User GuideGigE Mode`define count 3'd4`define txk 3'd5module gige8b10btest(clk

6–40 Altera CorporationStratix GX Transceiver User Guide January 2005Design Exampleif(kcntr==4'd11 || reset==1'b1)kcntr<=4'b0;els

Altera Corporation 6–41January 2005 Stratix GX Transceiver User GuideGigE Modebeginreset<=1;txctrl<=0;txdata<=datacntr;end`donothing: //

6–42 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExampleALTGXBmodule gige8b10bgxb (pll_areset,pllenable,inclk,rx_in,rx_s

Altera Corporation 6–43January 2005 Stratix GX Transceiver User GuideGigE Modewire [0:0] tx_out = sub_wire2[0:0];wire [0:0] rx_ctrldetect = sub_wi

6–44 Altera CorporationStratix GX Transceiver User Guide January 2005Design Examplealtgxb_component.preemphasis_ctrl_setting = 0,altgxb_component.l

Altera Corporation 6–45January 2005 Stratix GX Transceiver User GuideGigE ModeFigure 6–35. GigE Synchronization Sequence Quartus II Software Simul

Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ig

2–2 Altera CorporationStratix GX Transceiver User Guide January 2005Transmitter AnalogFigure 2–1. Block Diagram Analog ComponentsTransmitter Analog

6–46 Altera CorporationStratix GX Transceiver User Guide January 2005Design Example

Altera Corporation 7–1January 2005 7. Loopback ModesIntroductionYou can apply several loopback modes to the Stratix®GX block. The main forms of

7–2 Altera CorporationStratix GX Transceiver User Guide January 2005Parallel LoopbackFigure 7–1. Stratix GX Block in Serial Loopback Mode Parallel

Altera Corporation 7–3January 2005 Stratix GX Transceiver User GuideLoopback ModesFigure 7–2. Stratix GX Block in Parallel Loopback ModeReverse Se

7–4 Altera CorporationStratix GX Transceiver User Guide January 2005Reverse Serial LoopbackFigure 7–3. Stratix GX Block in Reverse Serial Loopback

Altera Corporation 8–1January 2005 8. Stratix GX Built-In Self Test(BIST)IntroductionEach Stratix®GX channel in the gigabit transceiver block c

8–2 Altera CorporationStratix GX Transceiver User Guide January 2005Pattern GeneratorFigure 8–2. Block Diagram of BIST ModesPattern GeneratorThe BI

Altera Corporation 8–3January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)PRBS mode is enabled when the PRBS option

8–4 Altera CorporationStratix GX Transceiver User Guide January 2005Pattern Generatordeterministic data dependant components are masked out. Howeve

Altera Corporation 8–5January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)Low-frequency mode is enabled when you sel

Altera Corporation 2–3January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionProgrammable Voltage Output Differential (VOD)Str

8–6 Altera CorporationStratix GX Transceiver User Guide January 2005Pattern VerifierBe sure you do not use the rx_apllreset signal because the re-t

Altera Corporation 8–7January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)Design ExamplesThe purpose of these design

8–8 Altera CorporationStratix GX Transceiver User Guide January 2005Design Examplesinput inclk;input rx_in;output coreclk_out;output tx_out;output

Altera Corporation 8–9January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)endmodulealtgxb Instantiation (PRBS_BIST.v

8–10 Altera CorporationStratix GX Transceiver User Guide January 2005Design Examples.tx_out (sub_wire0),.coreclk_out (sub_wire1),.rx_clkout (sub_wi

Altera Corporation 8–11January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)altgxb_component.data_rate = 3125,altgxb_

8–12 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExamplesFigure 8–5. Block Diagram of the Incremental BIST DesignTop-Lev

Altera Corporation 8–13January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST).coreclk_out(coreclk_out),.rx_bistdone(rx

8–14 Altera CorporationStratix GX Transceiver User Guide January 2005Design Examplesinput [0:0] inclk;input [0:0] rx_in;input [0:0] rx_slpbk;inp

Altera Corporation 8–15January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)altgxb_component.lpm_type = "altgxb&

2–4 Altera CorporationStratix GX Transceiver User Guide January 2005Transmitter AnalogYou can set the differential VOD values statically during con

8–16 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExamplesFigure 8–6. SignalTap II Results for PRBS BIST Test Design (Res

Altera Corporation 8–17January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)altgxb_component.pll_inclock_period = 625

8–18 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExamplesFigure 8–7. High-Frequency BIST Measured on tx_out[]Design 4: L

Altera Corporation 8–19January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)altgxb altgxb_component (inclk (inclk),.t

8–20 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExamplesFigure 8–8. Low-Frequency BIST Measured on tx_out[]Design 5: Mi

Altera Corporation 8–21January 2005 Stratix GX Transceiver User GuideStratix GX Built-In Self Test (BIST)altgxb altgxb_component (inclk (inclk),.t

8–22 Altera CorporationStratix GX Transceiver User Guide January 2005Design ExamplesFigure 8–9. Mix-Frequency BIST Measured on tx_out[]

Altera Corporation 9–1January 2005 9. Reset Control &Power DownIntroductionStratix®GX transceivers offer multiple reset signals to control

9–2 Altera CorporationStratix GX Transceiver User Guide January 2005USER Reset & Enable SignalsThe rxanalogreset signal is a power-down signal

Altera Corporation 9–3January 2005 Stratix GX Transceiver User GuideReset Control & Power DownIn 16-bit or 20-bit mode, asserting rxdigitalres

Altera Corporation 2–5January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionAs with the VOD settings, you can set the pre-emp

9–4 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsRecommended ResetsThe following reset recommendations help gu

Altera Corporation 9–5January 2005 Stratix GX Transceiver User GuideReset Control & Power DownFigure 9–3 shows a situation in which you must r

9–6 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsThe waveform in Figure 9–4 shows the functionality of the rec

Altera Corporation 9–7January 2005 Stratix GX Transceiver User GuideReset Control & Power DownDesign Example 1 This design example shows inclk

9–8 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets receive_digitalreset, pll_locked, rx_freqlocked,pll_areset,

Altera Corporation 9–9January 2005 Stratix GX Transceiver User GuideReset Control & Power Downalways @ (posedge inclk or posedge async_reset)

9–10 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsstate <= STROBE_TXPLL_LOCKED;rxdigitalreset_inclk <= 1

Altera Corporation 9–11January 2005 Stratix GX Transceiver User GuideReset Control & Power Down pll_areset <= 1'b0;endelse beginwaitst

9–12 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetselsebeginrxdigitalreset_rx_coreclk_Q <= rxdigitalreset_in

Altera Corporation 9–13January 2005 Stratix GX Transceiver User GuideReset Control & Power DownTransmit and Receive : Both usedDatapath : Sin

2–6 Altera CorporationStratix GX Transceiver User Guide January 2005Transmitter AnalogFigure 2–4. Transmitter PLL Block DiagramTable 2–2 lists some

9–14 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsreg rxdigitalreset_rx_clkout_Q;reg rxanalogreset_rx_clkout_Q

Altera Corporation 9–15January 2005 Stratix GX Transceiver User GuideReset Control & Power Downbeginrxdigitalreset_inclk <= 1'b1;rxana

9–16 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetspll_areset <= 1'b1;state <= STROBE_TXPLL_LOCKED;e

Altera Corporation 9–17January 2005 Stratix GX Transceiver User GuideReset Control & Power Down pld clock domain(Generic name, can be any cloc

9–18 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsFigure 9–5. Receiver & Transmitter With No Train Receive

Altera Corporation 9–19January 2005 Stratix GX Transceiver User GuideReset Control & Power DownFigure 9–6. Transmitter Reset SequenceThe wavef

9–20 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsFigure 9–7. Transmitter Reset Sequence WaveformFigure 9–8 sh

Altera Corporation 9–21January 2005 Stratix GX Transceiver User GuideReset Control & Power DownFigure 9–8. Receiver Reset SequenceThe waveform

9–22 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsFigure 9–9. Receiver Reset Sequence WaveformDesign Example 1

Altera Corporation 9–23January 2005 Stratix GX Transceiver User GuideReset Control & Power DownContacting Altera=================We have made

Altera Corporation 2–7January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionIf the reference clock exceeds 325 MHz, the clock

9–24 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsoutput rxdigitalreset;//GXB Receive digital reset output rxa

Altera Corporation 9–25January 2005 Stratix GX Transceiver User GuideReset Control & Power DownSTROBE_TXPLL_LOCKED: if (sync_reset) //Sy

9–26 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsbeginwaitstate_timer <= waitstate_timer;if(receive_digita

Altera Corporation 9–27January 2005 Stratix GX Transceiver User GuideReset Control & Power DownendendendmoduleDesign Example 2This design exam

9–28 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets************************************************************

Altera Corporation 9–29January 2005 Stratix GX Transceiver User GuideReset Control & Power Downparameter STABLE_TX_PLL = 3'b010;//Paramet

9–30 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsbeginstate <= STROBE_TXPLL_LOCKED;txdigitalreset <= 1&

Altera Corporation 9–31January 2005 Stratix GX Transceiver User GuideReset Control & Power Downrxdigitalreset_rx_cruclk <= 1'b1;endend

9–32 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsReceiver ResetThe configurations and design examples in this

Altera Corporation 9–33January 2005 Stratix GX Transceiver User GuideReset Control & Power DownFigure 9–11. Receiver Reset SequenceThe wavefor

2–8 Altera CorporationStratix GX Transceiver User Guide January 2005Transmitter AnalogA high-bandwidth setting provides a faster lock time and trac

9–34 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsf See the Stratix GX FPGA Family data sheet for the value of

Altera Corporation 9–35January 2005 Stratix GX Transceiver User GuideReset Control & Power Down/* Copyright (c) Altera Corporation, 2004. This

9–36 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsoutput rxdigitalreset;//GXB Receive digital reset output rxa

Altera Corporation 9–37January 2005 Stratix GX Transceiver User GuideReset Control & Power Downbeginrxdigitalreset_inclk <= 1'b0;rxana

9–38 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets rxanalogreset_inclk <= 1'b0; pll_areset <= 1&ap

Altera Corporation 9–39January 2005 Stratix GX Transceiver User GuideReset Control & Power Down/*synchronizing the rxdigitalreset to recovered

9–40 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets In this example, whenever the rx_freqlocked signal toggles

Altera Corporation 9–41January 2005 Stratix GX Transceiver User GuideReset Control & Power Downinput sync_reset; //Input: synchronous res

9–42 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsrxanalogreset_inclk <= 1'b1;pll_areset <= 1'

Altera Corporation 9–43January 2005 Stratix GX Transceiver User GuideReset Control & Power Downwaitstate_timer <= waitstate_timer - 1'

Altera Corporation 2–9January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionFigure 2–6. Serializer Bit OrderReceiver Analog T

9–44 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets pll_areset <= 1'b0;waitstate_timer <= WAITSTATE

Altera Corporation 9–45January 2005 Stratix GX Transceiver User GuideReset Control & Power DownThe difference in this configuration from the c

9–46 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets If you plan to use REFCLKB pins in your design, see Append

Altera Corporation 9–47January 2005 Stratix GX Transceiver User GuideReset Control & Power Downoutput rxdigitalreset;//GXB Receive digital res

9–48 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsbeginwaitstate_timer <= waitstate_timer - 1'b1;rxdig

Altera Corporation 9–49January 2005 Stratix GX Transceiver User GuideReset Control & Power DownDesign Example 2This design example shows a rec

9–50 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resets`timescale 1ns/10psmodule reset_seq_rx_rx_cruclk_rx_clkout (

Altera Corporation 9–51January 2005 Stratix GX Transceiver User GuideReset Control & Power Downendelsebeginif(sync_reset)beginrxanalogreset &l

9–52 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsalways @(posedge rx_clkout or posedge async_reset)if(async_r

Altera Corporation 9–53January 2005 Stratix GX Transceiver User GuideReset Control & Power DownFigure 9–14. Transmitter Only Clock OptionsFigu

2–10 Altera CorporationStratix GX Transceiver User Guide January 2005Receiver AnalogFigure 2–8. Receiver Input BufferProgrammable Receiver Terminat

9–54 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended ResetsThe waveform in Figure 9–16 shows the functionality of the t

Altera Corporation 9–55January 2005 Stratix GX Transceiver User GuideReset Control & Power Down If you plan to use REFCLKB pins in your desig

9–56 Altera CorporationStratix GX Transceiver User Guide January 2005Recommended Resetsoutput txdigitalreset; //GXB transmit digital resetoutput pl

Altera Corporation 9–57January 2005 Stratix GX Transceiver User GuideReset Control & Power Downelse if (pll_locked)begin state <= IDLE; txd

9–58 Altera CorporationStratix GX Transceiver User Guide January 2005Power DownPMA loop backSerial loop backTr i- sta te (4)toggleLow (5) ——Revers

Altera Corporation A–1January 2005 Appendix A. Data & ControlCodes8B/10B CodeThis appendix provides information about the data and control

A–2 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B CodeFigure A–2. 10-Bit Grouping of 6-Bit & 4-Bit Sub-BlocksThe runni

Altera Corporation A–3January 2005 Stratix GX Transceiver User GuideSupported CodesThe 8B/10B scheme defines the 12 control codes listed in Table

A–4 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B CodeD9.0 09 000 01001 100101 1011 100101 0100D10.0 0A 000 01010 010101 1

Altera Corporation A–5January 2005 Stratix GX Transceiver User GuideD10.1 2A 001 01010 010101 1001 010101 1001D11.1 2B 001 01011 110100 1001 11010

Altera Corporation 2–11January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionIf external termination is used, the receiver mu

A–6 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B CodeD11.2 4B 010 01011 110100 0101 110100 0101D12.2 4C 010 01100 001101

Altera Corporation A–7January 2005 Stratix GX Transceiver User GuideD12.3 6C 011 01100 001101 1100 001101 0011D13.3 6D 011 01101 101100 1100 10110

A–8 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B CodeD13.4 8D 100 01101 101100 1101 101100 0010D14.4 8E 100 01110 011100

Altera Corporation A–9January 2005 Stratix GX Transceiver User GuideD14.5 AE 101 01110 011100 1010 011100 1010D15.5 AF 101 01111 010111 1010 10100

A–10 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B CodeD15.6 CF 110 01111 010111 0110 101000 0110D16.6 D0 110 10000 011011

Altera Corporation A–11January 2005 Stratix GX Transceiver User GuideD16.7 F0 111 10000 011011 0001 100100 1110D17.7 F1 111 10001 100011 0111 1000

A–12 Altera CorporationStratix GX Transceiver User Guide January 20058B/10B Code

Altera Corporation B–1January 2005 Appendix B. Ports &ParametersInput PortsTable B–1 lists the input ports of the Stratix®GX device.Table

B–2 Altera CorporationStratix GX Transceiver User Guide January 2005Input Portsrx_enacdet[]No Enables alignment to the programmed pattern.Input por

Altera Corporation B–3January 2005 Stratix GX Transceiver User Guiderx_locktodata[]No Control signal for transceiver block receiver PLL to lock th

Altera Corporation iii ContentsAbout This User Guide ... viiHow to Contac

2–12 Altera CorporationStratix GX Transceiver User Guide January 2005Receiver AnalogThis variation in frequency response yields data-dependant jitt

B–4 Altera CorporationStratix GX Transceiver User Guide January 2005Input Portstx_vodctrl[]No 3-bit control signal that dynamically specifies the V

Altera Corporation B–5January 2005 Stratix GX Transceiver User GuideOutput PortsTable B–2 lists the output ports of the Stratix GX device.Table B–

B–6 Altera CorporationStratix GX Transceiver User Guide January 2005Output Portsrx_clkout[]No Output clock from the transceiver block receiver chan

Altera Corporation B–7January 2005 Stratix GX Transceiver User Guiderx_freqlocked[]No Indicates whether transceiver block receiver channel is lock

B–8 Altera CorporationStratix GX Transceiver User Guide January 2005Output Portsrx_errdetect[]No Indicates whether the 8B/10B decoder detects an er

Altera Corporation B–9January 2005 Stratix GX Transceiver User GuideParameter DescriptionsTable B–3 describes the Stratix GX device parameters.Tab

B–10 Altera CorporationStratix GX Transceiver User Guide January 2005Parameter DescriptionsPLL_INCLOCK_PERIODInteger Yes Specifies, in picoseconds

Altera Corporation B–11January 2005 Stratix GX Transceiver User GuideRUN_LENGTHInteger No Specifies the maximum run length supported for the incom

B–12 Altera CorporationStratix GX Transceiver User Guide January 2005Parameter DescriptionsSELF_TEST_MODEInteger NoIndicates which self test mode t

Altera Corporation B–13January 2005 Stratix GX Transceiver User GuideVOD_CTRL_SETTINGInteger No Specifies, in mV, the value of the VOD control sig

Altera Corporation 2–13January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionThe receiver PLL contains an optional loss-of-lo

B–14 Altera CorporationStratix GX Transceiver User Guide January 2005Parameter DescriptionsCONSIDER_INSTANTIATE_TRANSMITTER_PLLString No Specifies

Altera Corporation C–1January 2005 Appendix C. REFCLKB PinConstraintsKnown IssuesThis document discusses issues you might encounter in certain

C–2 Altera CorporationStratix GX Transceiver User Guide January 2005Known IssuesIf the design is using the transmitter PLL output to drive any cloc

Altera Corporation C–3January 2005 Stratix GX Transceiver User GuideQuartus II Software MessagesThe following sections provide details on the feed

C–4 Altera CorporationStratix GX Transceiver User Guide January 2005Known IssuesQuartus II Software Versions 4.0 SP1 & 4.1 For configurations 1

Altera Corporation C–5January 2005 Stratix GX Transceiver User Guide Error: XGMII GXB_RX:GXB_RX_a|CUSTOM_RX:CUSTOM_RX_inst|altgxb:altgxb_componen

C–6 Altera CorporationStratix GX Transceiver User Guide January 2005Known IssuesThe equivalent INI setting isasm_skip_gxb_clock_fanout_restriction

Altera Corporation C–7January 2005 Stratix GX Transceiver User Guide You can use the REFCLKB pin on an unused transceiver block to bring in the c

C–8 Altera CorporationStratix GX Transceiver User Guide January 2005Known Issues

2–14 Altera CorporationStratix GX Transceiver User Guide January 2005Receiver Analogwhere the reference clock signal is divided by 2, yielding a 31

Altera Corporation 2–15January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionTable 2–5 lists the possible multiplication valu

2–16 Altera CorporationStratix GX Transceiver User Guide January 2005Receiver AnalogValid receiver bandwidth settings are low, medium, and high. Th

Altera Corporation 2–17January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionDuring the lock-to-reference mode, the frequency

2–18 Altera CorporationStratix GX Transceiver User Guide January 2005Receiver Analogor not the CRU is ready. When both signals are asserted, the rx

Altera Corporation 2–19January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionIf the data width is 8 or 16, set the legal run

2–20 Altera CorporationStratix GX Transceiver User Guide January 2005MegaWizard Analog FeaturesFigure 2–12. Deserializer Bit OrderMegaWizard Analog

Altera Corporation 2–21January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionFigure 2–13. MegaWizard Plug-In Manager - ALTGXB

iv Altera Corporation Contents Stratix GX Transceiver User GuideByte Serializer ...

2–22 Altera CorporationStratix GX Transceiver User Guide January 2005MegaWizard Analog FeaturesFigure 2–14. MegaWizard Plug-In Manager - ALTGXB (Pa

Altera Corporation 2–23January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionFigure 2–15. MegaWizard Plug-In Manager - ALTGXB

2–24 Altera CorporationStratix GX Transceiver User Guide January 2005MegaWizard Analog FeaturesFigure 2–16. MegaWizard Plug-In Manager - ALTGXB (Pa

Altera Corporation 2–25January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionFigure 2–17. MegaWizard Plug-In Manager - ALTGXB

2–26 Altera CorporationStratix GX Transceiver User Guide January 2005MegaWizard Analog FeaturesFigure 2–18. MegaWizard Plug-In Manager - ALTGXB (Pa

Altera Corporation 2–27January 2005 Stratix GX Transceiver User GuideStratix GX Analog DescriptionFigure 2–19. MegaWizard Plug-In Manager - ALTGXB

2–28 Altera CorporationStratix GX Transceiver User Guide January 2005MegaWizard Analog Features

Altera Corporation 3–1January 2005 3. Basic ModeIntroductionThe basic mode of the Stratix®GX device includes the following features: Serial da

3–2 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureFigure 3–1. Block Diagram of a Duplex Channel C

Altera Corporation 3–3January 2005 Stratix GX Transceiver User GuideBasic Modeword alignment circuit that is used in conjunction with the pattern

Altera Corporation v Contents ContentsChapter 6. GigE ModeIntroduction ...

3–4 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureA 10-bit pattern, 7-bit pattern, or 16-bit patt

Altera Corporation 3–5January 2005 Stratix GX Transceiver User GuideBasic ModeManual Alignment ModesThe Stratix GX device supports manual alignmen

3–6 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureFigure 3–5 shows an example of how the word ali

Altera Corporation 3–7January 2005 Stratix GX Transceiver User GuideBasic ModeThe byte boundary is locked after the first comma is detected and al

3–8 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver Architecturedeasserted and the A1 pattern is present on the

Altera Corporation 3–9January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–7. Example of How the Word Aligner Symbols Interact in Manu

3–10 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureFigure 3–8. 10-Bit to 8-Bit ConversionResetThe

Altera Corporation 3–11January 2005 Stratix GX Transceiver User GuideBasic ModeDisparity Error DetectorThe 8B/10B decoder can detect disparity err

3–12 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureFigure 3–9. Disparity ErrorControl DetectThe 8

Altera Corporation 3–13January 2005 Stratix GX Transceiver User GuideBasic ModeByte DeserializerThe byte deserializer module further reduces the s

vi Altera Corporation Contents Stratix GX Transceiver User GuideChapter 9. Reset Control &Power DownIntroduction ...

3–14 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Receiver ArchitectureFigure 3–11. Receiver Byte Deserialzer in 10/2

Altera Corporation 3–15January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–13. Receiver Byte Deserialzer Data Recovery in Logic Array

3–16 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Transmitter ArchitectureIn basic mode, if the RX_CLKOUT port is not

Altera Corporation 3–17January 2005 Stratix GX Transceiver User GuideBasic ModeIf the TX_CORECLK is not selected as an optional input transmitter

3–18 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode Transmitter ArchitectureFor additional information regarding the 8B

Altera Corporation 3–19January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–17 shows the reset behavior of the 8B/10B encoder. When in

3–20 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode ClockingAn example would be the invalid code encoding of a K24.1 (d

Altera Corporation 3–21January 2005 Stratix GX Transceiver User GuideBasic ModeOn the transmitter channel the output of the transmitter PLL, corec

3–22 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode ClockingThis configuration has an independent rx_cruclk that feeds

Altera Corporation 3–23January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–21. altgxb in Basic Mode With rx_coreclk & tx_coreclk

Altera Corporation viiPreliminaryAbout This User GuideHow to Contact AlteraFor the most up-to-date information about Altera® products, go to the Al

3–24 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode ClockingBasic Mode Inter-Transceiver Block ClockingThis section des

Altera Corporation 3–25January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–22. Example of a Multi-Transceiver Block Device to Transmi

3–26 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode ClockingAnother inter-transceiver block consideration is the select

Altera Corporation 3–27January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–23. Inter-Transceiver Line Connections for EP1SGX25 Device

3–28 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode ClockingFigure 3–24 shows the transceiver routing with respect to i

Altera Corporation 3–29January 2005 Stratix GX Transceiver User GuideBasic ModeBasic Mode MegaWizard Plug-InAltera recommends that the Stratix GX

3–30 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode MegaWizard Plug-InFigure 3–25. MegaWizard Plug-In Manager - ALTGXB

Altera Corporation 3–31January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–26. MegaWizard Plug-In Manager - ALTGXB (Page 4 of 9) - Ge

3–32 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode MegaWizard Plug-InFigure 3–27. MegaWizard Plug-In Manager - ALTGXB

Altera Corporation 3–33January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–28. MegaWizard Plug-In Manager - ALTGXB (Page 6 of 9) - Re

viii Altera CorporationPreliminaryTypographic Conventions Stratix GX Transceiver User GuideTypographic ConventionsThis document uses the typographic

3–34 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode MegaWizard Plug-InFigure 3–29. MegaWizard Plug-In Manager - ALTGXB

Altera Corporation 3–35January 2005 Stratix GX Transceiver User GuideBasic ModeFigure 3–30. MegaWizard Plug-In Manager - ALTGXB (Page 8 of 9) - Tr

3–36 Altera CorporationStratix GX Transceiver User Guide January 2005Basic Mode MegaWizard Plug-InFigure 3–31. MegaWizard Plug-In Manager - ALTGXB

Altera Corporation 4–1January 2005 4. SONET ModeIntroductionOne of the most common serial backplanes in the communications or telecom area is t

4–2 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Receiver ArchitectureFigure 4–1. Block Diagram of Transceiver Channe

Altera Corporation 4–3January 2005 Stratix GX Transceiver User GuideSONET Modeembedded word alignment circuit to use in conjunction with the patte

4–4 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Receiver ArchitectureManual SONET Alignment Mode (2 Consecutive 8-bi

Altera Corporation 4–5January 2005 Stratix GX Transceiver User GuideSONET ModeIn SONET mode, the byte boundary is locked after the first comma is

4–6 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Receiver ArchitectureFigure 4–4. Word Aligner Symbols Interacting in

Altera Corporation 4–7January 2005 Stratix GX Transceiver User GuideSONET Modecomma, the rx_patterndetect[] signal is asserted for one clock cycle

Altera Corporation 1–1January 2005 1. IntroductionIntroductionStratix®GX devices combine highly advanced 3.1875-gigabit-per-second (Gbps) four-

4–8 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Receiver ArchitectureByte DeserializerThe byte deserializer module f

Altera Corporation 4–9January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–7 demonstrates the alternate case of the finishing alignmen

4–10 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Receiver ArchitectureFigure 4–8. Receiver Byte Deserializer Data Re

Altera Corporation 4–11January 2005 Stratix GX Transceiver User GuideSONET Modefor the read clock. Refer to “SONET Mode Channel Clocking” on page

4–12 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode ClockingThe Transmitter Phase Compensation FIFO module is always us

Altera Corporation 4–13January 2005 Stratix GX Transceiver User GuideSONET ModeFigure 4–11. Default Configuration of altgxb in SONET ModeIn Figure

4–14 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode Clockingfrequency detector of the receiver PLL. For more informatio

Altera Corporation 4–15January 2005 Stratix GX Transceiver User GuideSONET ModeThe coreclk_out is the output from the transmitter PLL. A coreclk_o

4–16 Altera CorporationStratix GX Transceiver User Guide January 2005SONET Mode ClockingFigure 4–13. altgxb in SONET Mode With rx_coreclk & tx_

Altera Corporation 4–17January 2005 Stratix GX Transceiver User GuideSONET ModeSONET Mode Inter-Transceiver Block ClockingThis section provides gu