Altera UG-01080 podręczniki

Altera UG-01080 Podręcznik Użytkownika (702 strony)

Marka: Altera | Kategoria: Oprogramowanie | Rozmiar: 4.60 MB |

Spis treści

101 Innovation Drive

San Jose, CA 95134

Contents

Altera Corporation

Native Transceiver PHYs

Transceiver PHY Modules

Resetting the Transceiver PHY

File Name Description

Unsupported Features

Getting Started Overview

Design Flows

Specifying Parameters

Simulate the IP Core

10GBASE-R PHY IP Core

Arria V GT 10GBASE-R

Transceiver Protocol

General Option Parameters

10GBASE-R PHY Interfaces

10GBASE-R PHY Data Interfaces

Reset Control and Power Down

Signal Name Directio

1588 Delay Requirements

10GBASE-R Parameters

Reconfig

10BASE-KR PHY Interfaces

Daisy-Chain Interface Signals

Bit R/W Name Description

100

PMA Registers

103

PCS Registers

104

Creating a 10GBASE-KR Design

105

Editing a 10GBASE-KR MIF File

106

Send Feedback

107

Design Example

108

SDC Timing Constraints

109

Acronyms

109

UG-01080

110

Related Information

111

Item Description

111

Device Family Support

112

1GbE Parameters

113

Speed Detection Parameters

114

PHY Analog Parameters

115

1G/10GbE PHY Interfaces

116

2015.01.19

117

1G/10GbE PHY Data Interfaces

118

Serial Data Interface

121

123

Addr Bit R/W Name Description

124

1G/10 GbE GMII PCS Registers

127

Cntl &

131

Editing a 1G/10GbE MIF File

132

Creating a 1G/10GbE Design

133

Simulation Support

139

TimeQuest Timing Constraints

139

WAN Wide Area Network

140

XAUI PHY IP Core

141

XAUI PHY Release Information

142

Stratix V Devices

143

Parameterizing the XAUI PHY

143

XAUI PHY General Parameters

144

Name Value Description

145

XAUI PHY Analog Parameters

146

Advanced Options Parameters

148

XAUI PHY Configurations

149

XAUI PHY Ports

150

XAUI PHY Data Interfaces

151

SDR XGMII TX Interface

152

SDR XGMII RX Interface

153

XAUI Hard IP Core

154

Hard PCS

154

Soft PCS

154

Name Direction Description

157

Interlaken PHY IP Core

168

Parameter Value Description

170

Interlaken PHY Interfaces

173

Interlaken PHY PLL Interface

181

Preset C

198

PHY for PCIe (PIPE) Clocks

201

Signal Name

202

Direction Signal Name

202

PHY IP Core for PCI Express

204

Hard PCS and PMA

204

Phase 2 (Optional)

210

Phase 3 (Optional)

211

Custom PHY IP Core

214

Parameterizing the Custom PHY

216

Word Alignment Parameters

220

Rate Match FIFO Parameters

222

Byte Order Parameters

224

Analog Parameters

229

Presets for Ethernet

229

Interfaces

232

Configuration Bus Used Bits

234

Clock Interface

236

Optional Status Interface

237

Custom PHY PCS and PMA

241

Custom PHY IP Core Registers

242

Reset Controls –Manual Mode

243

Custom PCS

245

Dynamic Reconfiguration

246

Low Latency PHY IP Core

248

General Options Parameters

251

Additional Options Parameters

254

TX PLL (0–3)

258

(Refer to

258

Channel Interface

259

Low Latency PHY Interfaces

260

PMA and Light-Weight PCS

264

Data Rate (Mbps)

270

TX_tc lock_output

273

PDI O >R X_ deser

273

Serial Data Rate (Mbps)

277

Single-Width Double-Width

277

8-Bit 16-Bit 16-Bit 32-Bit

277

TX Data Word Description

285

RX Data Word Description

286

Deterministic PHY IP Core

291

Parameter Presets

301

Name Range Description

302

Parameter Range Description

304

PATTERN POLYNOMIAL

323

PCS-PMA Width

323

8-Bit 10-Bit 16-Bit 20-Bit

323

10G PCS Pattern Generators

340

Native PHY Common Interfaces

345

Standard PCS Interface Ports

351

Name Dir Synchronous to

353

Description

353

10G PCS Interface

356

10G PCS Interface Ports

357

×6/×N Bonded Clocking

367

Transceiver Bank

368

Slew Rate Settings

374

General Parameters

378

PMA Parameters

379

TX PMA Parameters

380

TX PLL Parameters

381

RX PMA Parameters

383

Standard PCS Parameters

385

Phase Compensation FIFO

387

Rate Match FIFO

390

Overview

484

Cyclone Device Family Support

485

Altera V-Series FPGA

520

Utilization

522

Embedded

529

Controller

529

Offset Cancellation

530

Duty Cycle Calibration

530

EyeQ Usage Example

536

Turning on Triggered DFE Mode

540

Channel Reconfiguration

550

PLL Reconfiguration

550

MIF Generation

554

MIF Format

555

Reduced MIF Creation

559

560

Direct Write Reconfiguration

561

Reconfiguration

565

Loopback Modes

575

Transceiver

576

Transceiver PHY Instance

579

Transceiver PHY

579

Reset Controller

579

Transceiver PLL Parameters

592

Transceiver PLL Signals

593

XCVR_IO_PIN_TERMINATION

596

XCVR_REFCLK_PIN_TERMINATION

597

XCVR_TX_SLEW_RATE_CTRL

597

XCVR_VCCR_ VCCT_VOLTAGE

598

CDR_BANDWIDTH_PRESET

598

PLL_BANDWIDTH_PRESET

599

XCVR_RX_DC_GAIN

599

XCVR_ANALOG_SETTINGS_PROTOCOL

599

XCVR_RX_COMMON_MODE_VOLTAGE

600

XCVR_RX_SD_ENABLE

601

XCVR_RX_SD_OFF

601

XCVR_RX_SD_ON

602

XCVR_RX_SD_THRESHOLD

602

XCVR_TX_COMMON_MODE_VOLTAGE

603

XCVR_TX_PRE_EMP_1ST_POST_TAP

603

XCVR_TX_RX_DET_ENABLE

603

XCVR_TX_RX_DET_MODE

604

XCVR_TX_VOD

604

XCVR_TX_VOD_PRE_EMP_CTRL_SRC

604

XCVR_RX_BYPASS_EQ_STAGES_234

606

XCVR_VCCA_VOLTAGE

607

XCVR_VCCR_VCCT_VOLTAGE

608

XCVR_TX_PRE_EMP_PRE_TAP_USER

615

XCVR_TX_PRE_EMP_2ND_POST_TAP

616

XCVR_TX_PRE_EMP_INV_2ND_TAP

616

XCVR_TX_PRE_EMP_INV_PRE_TAP

617

XCVR_TX_PRE_EMP_PRE_TAP

617

XCVR_TX_RX_DET_OUTPUT_SEL

618

XCVR_GT_IO_PIN_TERMINATION

628

XCVR_GT_RX_DC_GAIN

635

XCVR_GT_RX_CTLE

636

XCVR_GT_TX_PRE_EMP_ PRE_TAP

638

XCVR_GT_TX_VOD_MAIN_TAP

638

Transceivers

648

2013.12.20

650

Stratix IV GX Devices

651

Parameter Name

653

Comments

653

Custom PHY Width

659

Chapter Document

661

Changes Made

661

Date Document

676

How to Contact Altera

702

Altera UG-01080 Podręcznik Użytkownika (120 strony)

Marka: Altera | Kategoria: Oprogramowanie | Rozmiar: 2.79 MB |

Spis treści

User Guide

Contents

Chapter 7. Custom PHY IP Core

1. Introduction

PHY - Stratix V

Reset Controller

Transceiver

Channel PLL

Figure 1–4

Note to Table 1–2:

Transceiver PHY

Avalon-MM PHY Management

Serial Loopback

Unsupported Features

2. Getting Started

Specifying Parameters

Simulate the IP Core

3. 10GBASE-R PHY IP Core

Stratix V FPGA

Release Information

Device Family Support

Parameter Settings

Interfaces

SDR XGMII TX Interface

SDR XGMII RX Interface

Avalon-MM Interface

Status Interface

Clocks, Reset, and Powerdown

Table 3–12. Clock Signals

TimeQuest Timing Constraints

4. XAUI PHY IP Core

Configurations

PMA Channel Controller

(Optional)

■ 1–enables serial loopback

■ 0–disables serial loopback

5. Interlaken PHY IP Core

Interface

Avalon-ST TX Interface

Avalon-ST RX Interface

PLL Interface

TX and RX Serial Interface

Optional Clocks for Deskew

■ The simulation language

■ The name of your testbench

Simulation Testbench

Resource Utilization

PCI Express PIPE

Hard PCS and PMA

PHY Management Signals

PIPE Interface

■ 1'b0: -6 dB

■ 1'b1: -3.5 dB

Note to Table 6–8:

Transceiver Serial Interface

Simulation

7. Custom PHY IP Core

General Options

8B/10B Encoder and Decoder

Word Alignment

Rate Match FIFO

Byte Ordering

Custom PHY PCS and PMA

Custom PHY IP Core

Clock Interface

Optional Status Signals

Note to Table 7–14:

8. Low Latency PHY IP Core

Note to Table 8–3:

■ 0–0 dB

■ 1–3 dB

■ 2–6 dB

■ 3–9 dB

■ 4–12 dB

PMA and Light-Weight PCS

100

101

Serial Data Interface

102

Optional Status Interface

102

Controller

103

Parameter Differences

107

Port Differences

108

XAUI PHY

109

PCI Express PHY (PIPE)

112

Note to Table 10–4:

113

Custom PHY

116

Additional Information

117

Info–2 Additional Information

118

Revision History

118

■ Initial release

119

Info–4 Additional Information

120

Typographic Conventions

120

Altera UG-01080 Podręcznik Użytkownika (484 strony)

Marka: Altera | Kategoria: Oprogramowanie | Rozmiar: 7.64 MB |

Spis treści

User Guide

Contents

Chapter 6. XAUI PHY IP Core

Chapter 9. Custom PHY IP Core

ContentsContents vii

ContentsContents ix

Additional Information

1. Introduction

1–2 Chapter 1: Introduction

Avalon-MM PHY Management

1–4 Chapter 1: Introduction

Chapter 1: Introduction 1–5

Unsupported Features

2. Getting Started

Specifying Parameters

Simulate the IP Core

3. 10GBASE-R PHY IP Core

10GBASE-R protocol

Arria V GT 10GBASE-R

Transceiver Protocol

General Option Parameters

Interfaces

Clocks for Arria V GT Devices

Clocks for Arria V GZ Devices

Clocks for Stratix IV Devices

Clocks for Stratix V Devices

10GBASE-R PHY IP Core

Note to Table 4–3:

Speed Detection

Functional Description

Clock and Reset Interfaces

SDR XGMII interface:

Control and Status Interfaces

PHY Link Training

Daisy-Chain Mode

10GBASE-KR PHY 1GbE Registers

Creating a 10GBASE-KR Design

WAN Wide Area Network

Acronym Definition

1G/10GbE Release Information

10GBASE-R Parameters

1Gb Ethernet Parameters

1G/10GbE Registers

100

PMA Registers

101

PCS Registers

102

GMII PCS Registers

103

Sequencer

106

Cntl &

106

Creating a 1G/10GbE Design

107

Editing a MIF File

108

Design Examples

109

Dynamic Reconfiguration

110

Simulation

111

TimeQuest Timing Constraints

111

Acronyms

111

6. XAUI PHY IP Core

113

Release Information

114

Device Family Support

114

Devices

115

Parameterizing the XAUI PHY

115

General Parameters

116

Analog Parameters

117

Stratix IV Devices

118

Advanced Options Parameters

119

Configurations

120

Data Interfaces

122

SDR XGMII TX Interface

124

SDR XGMII RX Interface

124

XAUI Hard IP Core

125

Hard PCS

125

Soft PCS

125

TimeQuest Timing Cons

135

Interlaken PHY IP Core

137

Optional Port Parameters

140

Interfaces

141

Avalon-ST TX Interface

142

Avalon-ST RX Interface

144

TX and RX Serial Interface

147

PLL Interface

147

Optional Clocks for Deskew

148

Resource Utilization

154

General Options Parameters

155

s window for Gen1 or Gen2

160

s window for Gen1

160

Figure 8–4 illustrates the

162

Optional Status Interface

163

Serial Data Interface

164

PHY IP Core for PCI Express

165

Hard PCS and PMA

165

Phase 2 (Optional)

170

Phase 3 (Optional)

171

9. Custom PHY IP Core

175

Custom PHY IP Core

176

Stratix V FPGA

176

Word Alignment Parameters

181

Rate Match FIFO Parameters

182

Byte Order Parameters

183

SOP to a different byte lane

184

IP Core

186

Presets for Ethernet

187

RX interface

190

Clock Interface

191

Custom PHY PCS and PMA

193

10. Low Latency PHY IP Core

199

 (PCS-PMA interface width)

202

Additional Options Parameters

203

PMA and Light-Weight PCS

210

Auto-Negotiation

216

Note to Figure11–2:

217

Delay Estimation Logic

219

Delay Numbers

220

 the number of bits

230

Deterministic PHY IP Core

232

Parameter Presets

241

PMA Parameters

243

TX PMA Parameters

244

TX PLL<n>

245

RX CDR Options

246

PMA Optional Ports

246

Standard PCS Parameters

249

Phase Compensation FIFO

250

Rate Match FIFO

253

10G PCS Parameters

257

10G TX FIFO

258

Stratix V Devices

259

100 ppm

260

Interlaken Frame Generator

262

Interlaken Frame Synchronizer

263

s period

265

s period, the

265

64b/66b Encoder and Decoder

266

96-bit bound. It adds the 67

267

Common Interface Ports

270

Standard PCS Interface Ports

273

10G PCS Interface

276

SDC Timing Constraints

284

Simulation Support

286

RX PMA Parameters

292

Arria V Devices

299

Cyclone V Devices

368

Controller IP Core

379

Altera V-Series FPGA

381

500 400 0 0 100

383

 4.9152 Gbps

387

Embedded

389

Controller

389

Offset Cancellation

390

Duty Cycle Calibration

390

PMA Analog Control Registers

391

7’h0C [6:0] RW

391

EyeQ Registers

392

DFE Registers

394

(Part 1 of 2)

395

address to 0x0

396

(Part 2 of 2)

396

address of 0xB

397

AEQ Registers

399

ATX PLL Calibration Registers

400

PLL Reconfiguration

401

Transceiver PHYs

402

PLL Reconfiguration Registers

403

7’h44 [15:0] RW

403

Channel Reconfiguration

405

Streamer Module Registers

406

When the

407

408

MIF Generation

409

MIF Format

410

Arguments:

412

-h: Displays help

412

Reduced MIF Creation

413

414

415

Figure 16–6. Sample MIF

418

Example 16–11. (continued)

419

Loopback Modes

427

Transceiver

428

Transceiver PHY Instance

429

Transceiver PHY

429

Reset Controller

429

Assignments

437

455

Transceivers

456

Stratix V GX/GS devices

458

Note to Table 19–3:

459

Note to Table 19–5:

462

Note to Table 19–7:

465

Revision History

468

s for Gen2 operation

476

address

480

Note to Table:

482

Typographic Conventions

483

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