Altera ALTPLL (Phase-Locked Loop) IP Core Instrukcja Użytkownika Pobierz pdf (Strona 45)

DescriptionConditionPort Name

(7)

The data output for the serial scan

chain. You can use the

scandataout port to determine

when PLL reconfiguration is

completed. The last output is

cleared when reconfiguration

completes. Not available for

Cyclone and Cyclone II devices.

Optionalscandataout

This output port indicates that the

scan chain write operation is

initiated. The scandone port goes

high when the scan chain write

operation initiates, and goes low

when the scan chain write

operation completes. Not available

for Cyclone, Cyclone II, Stratix,

and Stratix GX devices.

Optionalscandone

Serial clock output port.

This port is available only when

the PLL is in LVDS mode. Only

available for Arria GX, HardCopy

II, Stratix II, and Stratix II GX

devices.

Optionalsclkout[]

This output port indicates that the

VCO frequency has exceeded the

legal VCO range.

Optionalvcounverrange

This output port indicates that the

VCO frequency has not met the

legal VCO range.

Optionalvcounderrange

(7)

Replace the brackets, [], in the port name with an integer to get the exact name (for example, c0, c1, c3, e0,

e1, e2, enable1 and sclkout0).

Altera Corporation

ALTPLL (Phase-Locked Loop) IP Core User Guide

Send Feedback

ALTPLL Output Ports

ug-altpll

2014.08.18

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 68 69

Komentarze do niniejszej Instrukcji

Brak uwag

Altera ALTPLL (Phase-Locked Loop) IP Core Instrukcja Użytkownika Strona 45

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera ALTPLL (Phase-Locked Loop) IP Core