Altera Arria V GT FPGA Instrukcja Użytkownika

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Strona 1 - User Guide

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01124-1.0 User GuideArria V GT FPGA Development KitFeedback SubscribeArria V GT FPGA Developme

Strona 2

2–2 Chapter 2: Getting StartedReferencesArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideReferencesUse the following links to

Strona 3 - Contents

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide3. Software InstallationThis chapter explains how to install the following s

Strona 4

3–2 Chapter 3: Software InstallationInstalling the Quartus II Subscription Edition SoftwareArria V GT FPGA Development Kit November 2012 Altera Corpor

Strona 5 - Additional Information

Chapter 3: Software Installation 3–3Installing the Development KitNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideInstalling

Strona 6

3–4 Chapter 3: Software InstallationInstalling the USB-Blaster II DriverArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideInst

Strona 7 - 1. About This Kit

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide4. Development Board SetupThe instructions in this chapter explain how to se

Strona 8 - Kit Features

4–2 Chapter 4: Development Board SetupFactory Default Switch and Jumper SettingsArria V GT FPGA Development Kit November 2012 Altera CorporationUser G

Strona 9 - 2. Getting Started

Chapter 4: Development Board Setup 4–3Factory Default Switch and Jumper SettingsNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser G

Strona 10 - References

4–4 Chapter 4: Development Board SetupFactory Default Switch and Jumper SettingsArria V GT FPGA Development Kit November 2012 Altera CorporationUser G

Strona 11 - 3. Software Installation

Chapter 4: Development Board Setup 4–5Factory Default Switch and Jumper SettingsNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser G

Strona 12

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar

Strona 13 - <version>

4–6 Chapter 4: Development Board SetupFactory Default Switch and Jumper SettingsArria V GT FPGA Development Kit November 2012 Altera CorporationUser G

Strona 14

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide5. Board Update PortalThe Arria V GT FPGA Development Kit ships with the Boa

Strona 15 - 4. Development Board Setup

5–2 Chapter 5: Board Update PortalUsing the Board Update Portal to Update User DesignsArria V GT FPGA Development Kit November 2012 Altera Corporation

Strona 16

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide6. Board Test SystemThe kit includes a design example and an application cal

Strona 17 - Note to: Table 4–1

6–2 Chapter 6: Board Test SystemPreparing the BoardArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideSeveral designs are provi

Strona 18

Chapter 6: Board Test System 6–3Running the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideRunning the Boa

Strona 19 - Note to: Table 4–5

6–4 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide2. On the Configu

Strona 20

Chapter 6: Board Test System 6–5Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide PSO—Sets the MA

Strona 21 - 5. Board Update Portal

6–6 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe GPIO FPGA 1 T

Strona 22

Chapter 6: Board Test System 6–7Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideUser DIP SwitchTh

Strona 23 - 6. Board Test System

November 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideContentsChapter 1. About This KitKit Features . . . . . . . . . . . . . .

Strona 24 - Preparing the Board

6–8 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe following sec

Strona 25 - Using the Board Test System

Chapter 6: Board Test System 6–9Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideThe HSMA TabThe H

Strona 26 - The System Info Tab

6–10 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuidePort (FPGA1)The

Strona 27 - JTAG Chain

Chapter 6: Board Test System 6–11Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide LF —lowest fre

Strona 28 - The GPIO FPGA 1 Tab

6–12 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe SFP/SMA/C2C

Strona 29 - The Flash Tab

Chapter 6: Board Test System 6–13Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide Pattern sync—S

Strona 30

6–14 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide PRBS23—Selects

Strona 31 - The HSMA Tab

Chapter 6: Board Test System 6–15Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideThe HSMB/FMC Tab

Strona 32 - Data Type

6–16 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuidePort (FPGA2)The

Strona 33 - Loopback

Chapter 6: Board Test System 6–17Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide LF HSMB—lowest

Strona 34 - The SFP/SMA/C2C Tab

iv ContentsArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideFlash Memory Map . . . . . . . . . . . . . . . . . . . . . . . .

Strona 35

6–18 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe SDI/Bull’s E

Strona 36

Chapter 6: Board Test System 6–19Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuidePort (FPGA2)The

Strona 37 - The HSMB/FMC Tab

6–20 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideError ControlThi

Strona 38 - Port (FPGA2)

Chapter 6: Board Test System 6–21Using the Board Test SystemNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideThe SMA TabThe S

Strona 39

6–22 Chapter 6: Board Test SystemUsing the Board Test SystemArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuidePort (FPGA2)The

Strona 40 - The SDI/Bull’s Eye Tab

Chapter 6: Board Test System 6–23The Power MonitorNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideError ControlThis control

Strona 41

6–24 Chapter 6: Board Test SystemThe Power MonitorArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe Power Monitor communic

Strona 42

Chapter 6: Board Test System 6–25The Power MonitorNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser Guidef A table with the power r

Strona 43 - The SMA Tab

6–26 Chapter 6: Board Test SystemThe Clock ControlArria V GT FPGA Development Kit November 2012 Altera CorporationUser GuideThe Clock ControlThe Clock

Strona 44

Chapter 6: Board Test System 6–27Configuring the FPGA Using the Quartus II ProgrammerNovember 2012 Altera Corporation Arria V GT FPGA Development KitU

Strona 45 - The Power Monitor

Contents vNovember 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . .

Strona 46 - General Information

6–28 Chapter 6: Board Test SystemSamtec High-speed Bull’s Eye ConnectorArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide5. Cl

Strona 47 - Calculating Power

November 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideA. Programming the Flash MemoryDeviceAs you develop your own project using t

Strona 48 - The Clock Control

A–2 Appendix A: Programming the Flash Memory DevicePreparing Design Files for Flash ProgrammingArria V GT FPGA Development Kit November 2012 Altera Co

Strona 49

Appendix A: Programming the Flash Memory Device A–3Programming Flash Memory Using the Nios II EDSNovember 2012 Altera Corporation Arria V GT FPGA Deve

Strona 50

A–4 Appendix A: Programming the Flash Memory DeviceRestoring the Flash Device to the Factory SettingsArria V GT FPGA Development Kit November 2012 Alt

Strona 51 - CFI Flash Memory Map

Appendix A: Programming the Flash Memory Device A–5Restoring the MAX II CPLD to the Factory SettingsNovember 2012 Altera Corporation Arria V GT FPGA D

Strona 52

A–6 Appendix A: Programming the Flash Memory DeviceRestoring the MAX II CPLD to the Factory SettingsArria V GT FPGA Development Kit November 2012 Alte

Strona 53

November 2012 Altera Corporation Arria V GT FPGA Development KitUser GuideAdditional InformationThis chapter provides additional information about the

Strona 54 - ./restore.sh r

Info–2 Additional InformationTypographic ConventionsArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide“Subheading Title”Quotat

Strona 55

vi ContentsArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide

Strona 56

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide1. About This KitThe Altera® Arria®V GT FPGA Development Kit is a complete d

Strona 57

1–2 Chapter 1: About This KitKit FeaturesArria V GT FPGA Development Kit November 2012 Altera CorporationUser Guide1 After the year, your DKE license

Strona 58 - Typographic Conventions

November 2012 Altera Corporation Arria V GT FPGA Development KitUser Guide2. Getting StartedThe remaining chapters in this user guide lead you through

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