Altera Arria V GT FPGA Instrukcja Użytkownika Pobierz pdf (Strona 40)

6–18 Chapter 6: Board Test System

Using the Board Test System

Arria V GT FPGA Development Kit November 2012 Altera Corporation

User Guide

The SDI/Bull’s Eye Tab

The SDI/Bull’s Eye tab (Figure 6–8) allows you perform loopback tests on the Bull’s

Eye and SDI ports.

The following sections describe the controls on the SDI/Bull’s Eye tab.

Status

The Status control displays the following status information during the loopback test:

■ PLL lock—Shows the PLL locked or unlocked state.

■ Channel lock—Shows the channel locked or unlocked state. When locked, all

lanes are word aligned and channel bonded.

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

Figure 6–8. The SDI/Bull’s Eye Tab

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 57 58

Brak uwag

Altera Arria V GT FPGA Instrukcja Użytkownika Strona 40