Altera Arria V GX Starter Board Instrukcja Użytkownika Pobierz pdf (Strona 19)

Chapter 2: Board Components 2–11

MAX V CPLD 5M2210 System Controller

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

P10

MAX5_BEN0

2.5-V FSM bus MAX V byte enable 0

R11

MAX5_BEN1

2.5-V FSM bus MAX V byte enable 1

T12

MAX5_BEN2

2.5-V FSM bus MAX V byte enable 2

N11

MAX5_BEN3

2.5-V FSM bus MAX V byte enable 3

T11

MAX5_CLK

2.5-V FSM bus MAX V clock

R10

MAX5_CSN

2.5-V FSM bus MAX V chip select

M10

MAX5_OEN

2.5-V FSM bus MAX V output enable

N10

MAX5_WEN

2.5-V FSM bus MAX V write enable

E11

MAX_CONF_DONEN

2.5-V On-board USB-Blaster II configuration done LED

MAX_ERROR

2.5-V FPGA configuration error LED

MAX_LOAD

2.5-V FPGA configuration active LED

MAX_RESETN

2.5-V MAX V reset push button

B10

MSEL0

2.5-V FPGA mode select 0

MSEL1

2.5-V FPGA mode select 1

C10

MSEL2

2.5-V FPGA mode select 2

C12

MSEL3

2.5-V FPGA mode select 3

MSEL4

2.5-V FPGA mode select 4

OVERTEMP

2.5-V Temperature monitor fan enable

PCIE_JTAG_EN

2.5-V DIP switch to enable the PCI Express JTAG master

D12

PGM_CONFIG

2.5-V Load the flash memory image identified by the PGM LEDs

B14

PGM_LED0

2.5-V Flash memory PGM select indicator 0

C13

PGM_LED1

2.5-V Flash memory PGM select indicator 1

B16

PGM_LED2

2.5-V Flash memory PGM select indicator 2

B13

PGM_SEL

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

SDI_RX_BYPASS

2.5-V SDI equalization bypass

SDI_RX_EN

2.5-V SDI receive enable

D11

SDI_TX_EN

2.5-V SDI transmit enable

R12

SECURITY_MODE

2.5-V Reserved for future use

SENSE_CS0N

2.5-V Power monitor chip select

SENSE_SCK

2.5-V Power monitor SPI clock

SENSE_SDI

2.5-V Power monitor SPI data in

SENSE_SDO

2.5-V Power monitor SPI data out

SI571_EN

2.5-V Si571 programmable VCXO enable

USB_CFG0

2.5-V Reserved for future use

USB_CFG1

2.5-V Reserved for future use

USB_CFG2

2.5-V Reserved for future use

USB_CFG3

2.5-V Reserved for future use

USB_CFG4

2.5-V Reserved for future use

USB_CFG5

2.5-V Reserved for future use

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 6)

Board

Reference (U15)

Schematic Signal Name I/O Standard Description

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 61 62

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