Altera Arria V GX Starter Board Instrukcja Użytkownika Pobierz pdf (Strona 22)

2–14 Chapter 2: Board Components

FPGA Configuration

Arria V GX Starter Board November 2013 Altera Corporation

Reference Manual

The secondary method is to use the pre-built parallel flash loader (PFL) design

included in the development kit. The development board implements the Altera PFL

megafunction for flash memory programming. The PFL megafunction is a block of

logic that is programmed into an Altera programmable logic device (FPGA or CPLD).

The PFL functions as a utility for writing to a compatible flash memory device. This

pre-built design contains the PFL megafunction that allows you to write either page 0,

page 1, or other areas of flash memory over the USB interface using the Quartus II

software. This method is used to restore the development board to its factory default

settings.

Other methods to program the flash memory can be used as well, including the

Nios

II processor.

f For more information on the Nios II processor, refer to the Nios II Processor page of

the Altera website.

FPGA Programming from Flash Memory

On either power-up or by pressing the program configuration push button,

PGM_CONFIG

(S1), the MAX V CPLD 5M2210 System Controller's PFL configures the

FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash

memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then

written to the dedicated configuration pins in the FPGA during configuration.

Pressing the

PGM_CONFIG

push button (S1) loads the FPGA with a hardware page

based on which

PGM_LED[2:0]

LED (D11, D12, D13) illuminates.

Table 2–7 defines the design that loads when you press the

PGM_CONFIG

push button.

Table 2–7. PGM_LED Settings

(1)

PGM_LED0 PGM_LED1 PGM_LED2 Design

ON OFF OFF Factory

OFF ON OFF User design 1

OFF OFF ON User design 2

Note to Table 2–7:

(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.

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