Altera Arria V Hard IP for PCI Express Instrukcja Użytkownika Strona 10
- Strona / 288
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
1–2 Chapter 1: Datasheet
Features
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ Qsys support using the Avalon Memory-Mapped (Avalon-MM) with a 64- or
128-bit interface to the Application Layer
■ Extended credit allocation settings to better optimize the RX buffer space based on
application type.
■ Qsys example designs demonstrating parameterization, design modules and
connectivity.
■ Optional end-to-end cyclic redundancy code (ECRC) generation and checking and
advanced error reporting (AER) for high reliability applications.
■ Easy to use:
■ Easy parameterization.
■ Substantial on-chip resource savings and guaranteed timing closure.
■ Easy adoption with no license requirement.
■ New features in the 13.1 release
■ Added support for Gen2 Configuration via Protocol (CvP) using an .ini file.
Contact your sales representative for more information.
.The Arria V Hard IP for PCI Express offers different features for the variants that use
the Avalon-ST interface to the Application Layer and the variants that use an
Avalon-MM interface to the Application Layer. Variants using the Avalon-ST interface
are available in both the MegaWizard Plug-In Manager and the Qsys design flows.
Variants using the Avalon-MM interface are only available in the Qsys design flow.
Variants using the Avalon-ST interfaces offer a richer feature set; however, if you are
not familiar with the PCI Express protocol, variants using the Avalon-MM interface
may be easier to understand. A PCI Express to Avalon-MM bridge translates the PCI
Express read, write and completion TLPs into standard Avalon-MM read and write
commands typically used by master and slave interfaces. Table 1–1 outlines these
differences in features between variants with Avalon-ST and Avalon-MM interfaces to
the Application Layer.
Table 1–2. Differences in Features Available Using the Avalon-MM and Avalon-ST Interfaces (Part 1 of 2)
Feature Avalon-ST Interface Avalon-MM Interface
MegaCore License Free Free
Native Endpoint Supported Supported
Legacy Endpoint (1) Supported Not Supported
Root port Supported Supported
Gen1 ×1, ×2, ×4, and ×8 ×1, ×4, and ×8 (2)
Gen2 ×1, ×2, ×4 ×1, ×4 (2)
MegaWizard Plug-In Manager design flow Supported Not supported
Qsys design flow Supported Supported
64-bit Application Layer interface Supported Supported
128-bit Application Layer interface Supported Supported
- User Guide 1
- Contents 3
- Chapter 7. IP Core Interfaces 5
- Chapter 9. Reset and Clocks 5
- Chapter 18. Debugging 8
- 1. Datasheet 9
- 1–2 Chapter 1: Datasheet 10
- Features 10
- Notes to Table 1–1: 11
- Release Information 12
- Device Family Support 12
- Configurations 12
- Debug Features 13
- IP Core Verification 14
- Recommended Speed Grades 15
- 1–8 Chapter 1: Datasheet 16
- Qsys Design Flow 25
- Generating the Testbench 26
- Modifying the Example Design 34
- Running Qsys 36
- Table 3–5 38
- On Chip r 40
- Simulating the Example Design 44
- Direct BFM’s shared memory 47
- {*reconfig_xcvr_clk*} 50
- Compiling the Design 51
- Programming a Device 51
- System Settings 54
- Port Functions 55
- Error Reporting 57
- 31 19 18 17 16 15 14 58
- Power Management 59
- Legacy Interrupt 63
- Base Address Registers 66
- PCI Express/PCI Capabilities 67
- Header 68
- 6. IP Core Architecture 75
- Avalon-ST Interface 77
- RX Datapath 77
- TX Datapath 77
- Altera FPGA 77
- Clocks and Reset 78
- Interrupts 79
- Transaction Layer 79
- Protocol Layers 80
- Configuration Space 81
- Data Link Layer 81
- Figure 6–4. Data Link Layer 82
- Physical Layer 83
- Figure 6–5. Physical Layer 84
- Multi-Function Support 86
- PCI Express Avalon-MM Bridge 86
- Avalon-MM Bridge TLPs 88
- Figure 6–9. Poor Address Map 93
- RX Block 97
- Avalon-MM RX Master Block 97
- TX Block 98
- Interrupt Handler Block 98
- 7. IP Core Interfaces 99
- Note to Table 7–1: 100
- RX Port 101
- Avalon-ST RX Interface 103
- Note to Figure 7–7: 108
- Avalon-ST TX Interface 113
- Note to Table 7–4: 116
- ECRC Forwarding 121
- Clock Signals 121
- Reset Signals 122
- and the LTSSM L0 state 124
- ECC Error Signals 125
- Interrupts for Endpoints 125
- Interrupts for Root Ports 126
- Completion Side Band Signals 126
- Specification, Rev. 2.1 128
- D E F 0 1 2 3 131
- Notes to Table 7–13: 132
- LMI Signals 136
- LMI Read Operation 137
- LMI Write Operation 137
- Power Management Signals 138
- (Full-Featured Qsys) 140
- Completer-Only Single DWord 141
- RX Avalon-MM Master Signals 143
- Transceiver Reconfiguration 145
- Serial Interface Signals 145
- PIPE Interface Signals 149
- Test Signals 153
- Notes to Table 7–27: 154
- 8. Register Descriptions 155
- Note to Table 8–2: 156
- Note to Table 8–3: 157
- Note to Table 8–4: 157
- Note to Table 8–5: 157
- Note to Table 8–6: 158
- Note to Table 8–7: 158
- Note to Table 8–8: 159
- PCI Express Mailbox Registers 167
- Note to Table 8–30: 168
- Root Port TLP Data Registers 170
- Sending a TLP 173
- Receiving a Completion TLP 173
- Endpoints 174
- Avalon-MM Mailbox Registers 175
- Spec 2.1 176
- 9. Reset and Clocks 181
- Example Design 182
- Hard IP for PCI Express 182
- 127 cycles 184
- ±300 PPM 185
- Note to Table 9–2: 186
- Transceiver Clock Signals 187
- Supported Message Types 189
- Notes to Table 10–1: 191
- Receive Buffer Reordering 192
- Notes to Table 10–2: 193
- MSI Interrupts 195
- 11–2 Chapter 11: Interrupts 196
- Note to Figure 11–4: 197
- Legacy Interrupts 198
- Application Layer 199
- 11–6 Chapter 11: Interrupts 200
- MSI/MSI-X Support 201
- Qsys System 202
- 12. Optional Features 203
- ECRC on the RX Path 204
- ECRC on the TX Path 205
- 13. Flow Control 207
- 13–2 Chapter 13: Flow Control 208
- Throughput of Posted Writes 208
- Chapter 13: Flow Control 13–3 209
- 13–4 Chapter 13: Flow Control 210
- 14. Error Handling 211
- Physical Layer Errors 212
- Data Link Layer Errors 212
- Transaction Layer Errors 213
- Note to Table 14–4: 215
- Figure 15–2 218
- Core User Guide 219
- 16. SDC Timing Constraints 221
- Endpoint Testbench 224
- Root Port Testbench 225
- Chaining DMA Design Examples 226
- Root Complex 227
- Chaining DMA 227
- Hard IP for 227
- PCI Express 227
- Note to Table 17–2: 232
- Note to Table 17–4: 233
- Test Driver Module 236
- DMA Write Cycles 237
- DMA Read Cycles 239
- Root Port Design Example 240
- Root Port 241
- Variation 241
- (variation_name.v) 241
- Root Port BFM 242
- BFM Memory Map 244
- Figure 17–6 248
- BFM Read and Write Procedures 250
- BFM Procedures and Functions 251
- BFM Configuration Procedures 256
- Shared Memory Constants 257
- 18. Debugging 271
- 18–2 Chapter 18: Debugging 272
- Link Training 272
- Chapter 18: Debugging 18–3 273
- 18–4 Chapter 18: Debugging 274
- Chapter 18: Debugging 18–5 275
- Setting Up Simulation 276
- Chapter 18: Debugging 18–7 277
- Use Third-Party PCIe Analyzer 278
- BIOS Enumeration Issues 278
- Notes to Table A–7: 280
- Chapter : A–3 281
- Notes to Table A–16: 282
- Additional Information 283
- Info–2 Revision History 284
- How to Contact Altera 285
- Typographic Conventions 286
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Arria V Hard IP for PCI Express
(286 strony)© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.044 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji