Altera Cyclone II PowerPlay Early Power Estimator Instrukcja Użytkownika Strona 21

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Altera Corporation 3–5
May 2006 PowerPlay Early Power Estimator User Guide For Cyclone II FPGAs
Using the Cyclone II PowerPlay Early Power Estimator
Figure 3–2. TFF Example
Figure 3–3. 4-Bit Counter Example
Figure 3–4 shows the Resource Usage Summary in the Quartus II
software Compilation Report for a design targeting the Cyclone II device
family. The Compilation Report provides the total number of LUTs and
registers used by the design.
PRN
CLRN
TQ
TFF
clock
V
CC
INPUT
V
CC
OUTPUT
tff output
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
V
CC
V
CC
V
CC
V
CC
cout2
cout1
cout0
clock
cout3
OUTPUT
cout0cout0
OUTPUT
cout3cout3
OUTPUT
cout2cout2
OUTPUT
cout1cout1
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