Altera Cyclone V GT FPGA Instrukcja Użytkownika Pobierz pdf (Strona 43)

Chapter 6: Board Test System 6–21

The Clock Control

September 2014 Altera Corporation Cyclone V GT FPGA Development Kit

User Guide

Target Frequency

This control allows you to specify the frequency of the clock. Legal values are between

10 and 810 MHz with eight digits of precision to the right of the decimal point. For

example, 421.31259873 is possible within 100 parts per million (ppm). The Target

frequency control works in conjunction with the Set New Frequency control.

Clear

Sets the frequency for the oscillator associated with the active tab back to its default

value. This can also be accomplished by power cycling the board.

Set New Frequency

Sets the programmable oscillator frequency for the selected clock to the value in the

Target frequency control for the Si570 and Si571 oscillators. Frequency changes might

take several milliseconds to take effect. You might see glitches on the clock during this

time. Altera recommends resetting the FPGA logic after changing frequencies.

f For more information about the Si570/Si571 and the Cyclone V GT FPGA

development board’s clocking circuitry and clock input pins, refer to the Cyclone V GT

FPGA Development Board Reference Manual.

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Altera Cyclone V GT FPGA Instrukcja Użytkownika Strona 43