Altera DDR Timing Wizard Instrukcja Użytkownika Pobierz pdf (Strona 43)

Altera Corporation 2–31

November 2007 DDR Timing Wizard User Guide

Getting Started

Figure 2–22. Postamble Clock Connectivity

The postamble_sys_cycle and postamble_sys_phase are

specific to the fedback-clock mode implementation. The

postamble_sys_cycle information should match with the

number in the legacy controller MegaWizard. The

postamble_sys_phase, however, depends on whether the option

to use intermediate postamble registers is checked in the legacy

controller MegaWizard or not. When the option is checked,

postamble_sys_phase is set to 0

°. When the option is not checked

in the design, postamble_sys_phase is set to –180

°.

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 91 92

DDR Timing Wizard 1
Table of Contents 3
November 2007 4
About this User Guide 5
Typographic 6
Conventions 6
1. About the DDR Timing 7
Device Family 8
1–4 Altera Corporation 10
Introduction 10
Altera Corporation 1–5 11
About the DDR Timing Wizard 11
Note to Figure 1–1: 11
Features 12
2. Getting Started 13
Design Flow 14
2–2 Altera Corporation 14
Altera Corporation 2–3 15
Getting Started 15
2–4 Altera Corporation 16
Launching the 17
DDR Timing 17
Entering and 18
Editing Inputs to 18
Recommended Data Path 19
2–8 Altera Corporation 20
Altera Corporation 2–9 21
2–10 Altera Corporation 22
Altera Corporation 2–11 23
2–12 Altera Corporation 24
Altera Corporation 2–13 25
Synchronous Systems 26
Altera Corporation 2–15 27
(Figure 2–10) 28
Altera Corporation 2–17 29
2–18 Altera Corporation 30
Analysis & Synthesis 31
2–20 Altera Corporation 32
Altera Corporation 2–21 33
2–22 Altera Corporation 34
Click Next 35
2–24 Altera Corporation 36
Altera Corporation 2–25 37
2–26 Altera Corporation 38
Altera Corporation 2–27 39
2–28 Altera Corporation 40
Altera Corporation 2–29 41
Altera Corporation 2–31 43
200 MHz) 44
Altera Corporation 2–33 45
2–34 Altera Corporation 46
Altera Corporation 2–35 47
2–36 Altera Corporation 48
Altera Corporation 2–37 49
2–38 Altera Corporation 50
Altera Corporation 2–39 51
2–40 Altera Corporation 52
Altera Corporation 2–41 53
2–42 Altera Corporation 54
Altera Corporation 2–43 55
Click Finish 56
Altera Corporation 2–45 57
DTW Limitations 58
2–48 Altera Corporation 60
3. Using the 61
3–2 Altera Corporation 62
-dwz_file <value> 63
-? or -help 63
-after_iptb <value> 64
-auto_adjust_cycles 64
-extract_tcos <value> 64
*auk_ddr_datapath 65
*auk_qdrii_sram_datapath 65
*auk_rldramii_datapath 65
-stop_after <value> 66
-vwf_file_name <value> 66
-write_side 66
Altera Corporation 3–7 67
■ Timing Summary 67
Altera Corporation 3–9 69
■ Recommended Settings 69
Timing Closure 72
Altera Corporation 3–13 73
Note to Figure 3–6: 73
DDR2/DDR SDRAM Interfaces 74
QDRII+/QDRII SRAM Interfaces 74
RLDRAM II Interfaces 75
3–16 Altera Corporation 76
Timing Closure Process 76
Altera Corporation 3–17 77
Analyzer 78
Altera Corporation 3–19 79
3–20 Altera Corporation 80
Altera Corporation 3–21 81
3–22 Altera Corporation 82
Changing Clock Phase Shift 83
3–24 Altera Corporation 84
Altera Corporation 3–25 85
Changing Clock Cycles 87
3–28 Altera Corporation 88
Altera Corporation 3–29 89
3–30 Altera Corporation 90
° phase shift in 90
Altera Corporation 3–31 91
Conclusion 92

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