Altera Internal Memory (RAM and ROM) IP Core Instrukcja Użytkownika Strona 1

Embedded Memory (RAM: 1-PORT, RAM:2-PORT, ROM: 1-PORT, and ROM: 2-PORT)User GuideSubscribeSend FeedbackUG-010682014.12.17101 Innovation DriveSan Jose,

The new parameter editor appears when the generation is complete.4. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Ve

Embedded Memory Functional Description32014.12.17UG-01068SubscribeSend FeedbackDescribes the features and functionality of the embedded memory blocks

Table 3-1: Embedded Memory Blocks in Altera DevicesDeviceFamilyMemory Block TypeM512(512bits)(1)M4K (4Kbits)M-RAM(512Kbits) (2)MLAB(640 bits)(3)M9K (9

Embedded Memory Blocks Write Operation (4)Read OperationMLAB Falling clock edgesRising clock edges (in ArriaV, Cyclone V, and Stratix Vdevices only)Ri

Figure 3-2: Valid Write Operation that Triggers at Falling Clock EdgesThis figure assumes that twc is the maximum write cycle time interval. Write ope

Mixed-width Port ConfigurationOnly dual-port RAM and dual-port ROM support mixed-width port configuration for all memory blocktypes except when they a

Embedded Memory Blocks Valid Range (6)M144K 2K–16KM9K 256–8KMLAB 32–64 (7)M512 32–512M4K 128–4KM-RAM 4K–64KThe parameter editor prompts an error messa

Table 3-5: Clocking ModesThis table lists the embedded memory clocking modes.Clocking Modes Single-portRAMSimple Dual-port RAMTrue Dual-portRAMSingle-

Figure 3-4: Address Clock Enable During Read Cycle WaveformThis figure shows the address clock enable waveform during the read cycle. inclockrdenrdadd

You can specifically define and set the size of a byte for the byte-enable port. The valid values are 5, 8, 9,and 10, depending on the type of embedde

ContentsAbout RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORTIP Cores...

Asynchronous ClearThe embedded memory blocks in the Arria II GX, Arria II GZ, Stratix IV, Stratix V, and newer devicefamilies support the asynchronous

Memory Modes M9K, M144K, M10K, M20K MLABSimple dual-port RAM Supported —True dual-port RAM Supported —Tri-port RAM Supported —Single-port ROM Supporte

RDW Operation DescriptionMixed-PortRDWThe mixed-port RDW occurs when one port reads and another port writes to the sameaddress location with the same

Memory BlockTypesSingle-port RAM (9)Simple dual-portRAM (10)True dual-port RAMSame port RDW Mixed-port RDW Same port RDW (11)Mixed-port RDW (12)MLABDo

memory block being used, provided you do not assign block type when you instantiate the memoryblock.Power-Up Conditions and Memory InitializationPower

Error Correction CodeError correction code (ECC) allows you to detect and correct data errors at the output of the memory.The Stratix III and Stratix

Embedded Memory Signals and Parameters42014.12.17UG-01068SubscribeSend FeedbackDescribes the signals and parameters of the RAM: 1-PORT, RAM: 2-PORT, R

Signal Type Required Descriptionbyteena_a Input Optional Byte enable input to mask the data_a port so that onlyspecific bytes, nibbles, or bits of the

Signal Type Required Descriptionaddressstall_b Input Optional Address clock enable input to hold the previous address ofaddress_b port for as long as

Signal Type Required Descriptionclocken3 Input Optional Clock enable input for clock1 port.aclr0aclr1Input Optional Asynchronously clear the registere

Simulating the Design... 5-4Document

Signal Type Required Descriptionbyteena Input Optional Byte enable input to mask the data port so that onlyspecific bytes, nibbles, or bits of data ar

Signal Type Required Descriptionaclr Input Optional Asynchronously clear the registered input and outputports. The asynchronous clear effect on the re

Parameter Legal Values DescriptionWhich ports should be registered?The following options are available:• ‘data’ and ‘wren’ input ports• ‘address’ inpu

Parameter Legal Values DescriptionMore Options ‘q’ port On/Off Turn on this option for the ‘q’port to be affected by theasynchronous clear signal. The

RAM: 2-Port IP Core ParametersThis table lists the parameters for the RAM: 2-Port IP CoreTable 4-3: RAM: 2-Port Parameter SettingsParameter Legal Valu

Parameter Legal Values DescriptionSet the maximum block depth to Auto, 32, 64, 128,256, 512, 1024, 2048,4096Specifies the maximum blockdepth in words.

Parameter Legal Values DescriptionWhen you select With one read port and one writeport, the following option is available:Create a ‘rden’ read enable

Parameter Legal Values DescriptionWhich ports should be registered?When you select With one read port and one writeport, the following options are ava

Parameter Legal Values DescriptionMore OptionsWhen you selectWith one read portand one write port,the following optionis available:• Use clock enablef

Parameter Legal Values DescriptionMore OptionsWhen you selectWith one read portand one write port,the following optionsare available:• Create an ‘wr_a

About RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT IP Cores12014.12.17UG-01068SubscribeSend FeedbackThe Quartus® II software automatically s

Parameter Legal Values DescriptionWhen you select With one read port and one writeport, the following option is available:• How should the q output be

Parameter Legal Values DescriptionWhat should the ‘q_a’ output be when reading froma memory location being written to?• New data• Old DataSpecifies th

Parameter Legal Values DescriptionWhat should the memory block type be? Auto, M4K, M9K,M144K, M10K,M20KSpecifies the memory blocktype. The types of me

Parameter Legal Values DescriptionMore Options‘address’ port On/Off Specifies whether the‘address’ port should beaffected by the ‘aclr’ port.‘q’ port

Parameter Legal Values DescriptionUse different data widths on different ports On/Off Specifies whether to usedifferent data widths ondifferent ports.

Parameter Legal Values DescriptionWhat clocking method would you like to use?• Single clock• Dual clock: useseparate ‘input’and ‘output’clocks• Dual c

Parameter Legal Values DescriptionMore OptionsUse clock enable forport A inputregistersOn/Off Specifies whether to useclock enable for port A inputreg

Design Example52014.12.17UG-01068SubscribeSend FeedbackSimulate the designs using the ModelSim®-Altera software to generate a waveform display of the

is asserted. Because the RAM mode has two dedicated write ports, another encoder is implemented for theother RAM input port.Two ALTECC_DECODER blocks

Option ValueHow wide should the data be? 13 bitsDo you want to pipeline the functions? Yes, I want an output latency of 1 clock cycleCreate an 'a

Supported Memory Operation ModesThis table lists the supported memory operation mode and the related IP core for each operation mode.Table 1-2: Suppor

Option ValueGenerate netlist Turned offVariation file (.vhd) Turned onAHDL Include file (.inc) Turned offVHDL component declaration file (.cmp) Turned

Ports Name PortsTypeDescriptionsaddress_adata_awren_arden_aInput Address input, data input, write enable, and read enable toport A of the RAM. (17)add

Figure 5-2: Same-Port Read-During-WriteThis figure shows the timing diagram of when the same-port read-during-write occurs for each port Aand port B o

Figure 5-3: Mixed-Port Read-During-WriteThis figure shows the timing diagram of when the mixed-port read-during-write occurs.At 12500 ps, mixed-port r

Figure 5-4: Write ContentionThis figure shows the timing diagram of when the write contention occurs.At 22500 ps, the write contention occurs when dat

Figure 5-5: Error Injection– Asserting corrupt_dataa_bit0This figure shows the timing diagram of the effect when an error is injected to twist the LSB

Document Revision HistoryA2014.12.17UG-01068SubscribeSend FeedbackDocument Revision HistoryThis table lists the document revision history for the user

Date Version ChangesNovember 2012 4.1• Added a note to the “Asynchronous Clear” on page 3–15to state that internal contents cannot be cleared with the

Customizing Embedded Memory IP Cores22014.12.17UG-01068SubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many usef

IP Catalog and Parameter EditorThe Qsys IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrateIP cores into y

Figure 2-2: IP Parameter EditorsView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand tar

7. To generate an HDL instantiation template that you can copy and paste into your text editor, clickGenerate > HDL Example.8. Click Finish. The pa