Altera Nios Development Board Stratix II Edition Instrukcja Użytkownika Pobierz pdf (Strona 23)

Altera Corporation Reference Manual 2–13

May 2007 Nios Development Board Stratix II Edition

Board Components

Ethernet

MAC/PHY (U4) &

RJ45 Connector

(RJ1)

The LAN91C111 chip (U4) is a 10/100 Ethernet media access control and

physical interface (MAC/PHY) chip. The control pins of U4 are

connected to the FPGA so that Nios II systems can access Ethernet

networks via the RJ-45 connector (RJ1) as shown in Figure 2–4. The

Nios II development tools include hardware and software components

that allow Nios II processor systems to communicate with the

LAN91C111 Ethernet device.

Figure 2–4. Ethernet RJ-45 Connector

Refer to Table 2–9 for connections between the FPGA and the MAC/PHY

device.

1 The Ethernet MAC/PHY device shares both address and data

connections with the flash memory.

Table 2–9. Ethernet MAC/PHY Pin Table

FPGA Pin U4 Pin Pin Function Board Net Name (1)

AB25 41 Address Enable enet_aen

W20 43 Synchronous Ready enet_srdy_n

W19 40 VL Bus Access enet_vlbus_n

Y21 45 Local Device enet_ldev_n

Y20 38 IO Char Ready enet_iochrdy

AA22 37 Address Strobe enet_ads_n

AA21 42 Local Bus Clock enet_lclk

W26 46 Ready/Return enet_rdyrtn_n

AA26 35 Bus Cycle enet_cycle_n

AA25 36 Write/Read enet_w_r_n

W24 34 Bus Chip Select enet_datacs_n

W23 29 Interrupt enet_intr0

RJ1

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 61 62

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Altera Nios Development Board Stratix II Edition Instrukcja Użytkownika Strona 23