Altera Quartus II Scripting Instrukcja Użytkownika Pobierz pdf (Strona 455)

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101

Chapter 3: Tcl Packages & Commands 3–325

sdc_ext

derive_pll_clocks

Usage

derive_pll_clocks [-create_base_clocks] [-use_tan_name]

Options

-create_base_clocks: Creates base clocks on input clock ports of the design that are

feeding the PLL

-use_tan_name: Use net names as clock names

Description

Identifies PLLs or similar resources in the design and creates generated clocks for their output clock pins.

Multiple generated clocks may be created for each output clock pin if the PLL is using clock switchover,

one for the inclk[0] input clock pin and one for the inclk[1] input clock pin.

By default this command does not create base clocks on input clock ports that are driving the PLL. When

you use the create_base_clocks option, derive_pll_clocks also creates the base clock on an input clock port

deriving the PLL. This option does not overwrite an existing clock.

By default the clock name is the same as the output clock pin name. To use the net name (the same name

the classic Timing Analyzer would use), use the -use_tan_name option.

Example

project_open top

create_timing_netlist

# Create the base clock for the input clock port driving the PLL

create_clock -period 10.0 [get_ports sysclk]

# Create the generated clocks for the PLL.

derive_pll_clocks

update_timing_netlist

# Other user actions

report_timing

delete_timing_netlist

project_close

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