Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY Instrukcja Użytkownika Pobierz pdf (Strona 2)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY

User's Guide

Version 1.0 - October 2005

Contents

1 DESIGN KIT INSTALLATION.........................................................................................................3

1.1 PLATFORM SPECIFIC JAVA RUNTIME INSTALLATION ......................................................................3

1.2 DESIGN KIT INSTALLATION ............................................................................................................3

2 DESIGN FLOW................................................................................................................................4

3 GENERATING THE MAC/PHY CORE............................................................................................5

3.1 OVERVIEW ...................................................................................................................................5

3.2 CORE CONFIGURATION OPTIONS ..................................................................................................6

3.3 DESIGN KIT DATABASE .................................................................................................................7

3.4 SIMULATION ENVIRONMENT ..........................................................................................................7

3.5 RUNNING SIMULATION USING MODELSIM SE .................................................................................8

Overview..........................................................................................................................................8

Testbuilder Options..........................................................................................................................9

3.6 RUNNING SIMULATION USING MODELSIM PE OR MODELSIM AE....................................................13

Overview........................................................................................................................................13

Simulation Options.........................................................................................................................13

3.7 DESIGN IMPLEMENTATION WITH QUARTUS II ................................................................................16

3.8 VQM NETLIST GENERATION .......................................................................................................16

3.9 FULL TIMING GATE LEVEL SIMULATION ........................................................................................17

4 CONTACT .....................................................................................................................................18

List of Figures

Figure 1: Design Flow Overview.............................................................................................................5

Figure 2: MAC Core Configuration Panel ...............................................................................................6

Figure 3: Testbench Setup Overview......................................................................................................8

Figure 4: Running Testbuilder Overview.................................................................................................9

Figure 5: Testbuilder Panel...................................................................................................................10

Figure 6: VQM Netlist Generation.........................................................................................................17

List of Tables

Table 1: Core Configuration Options ......................................................................................................7

Table 2: Design Kit Directory Structure...................................................................................................7

Table 3: Simulation Options..................................................................................................................10

Table 4: MAC Configuration Options ....................................................................................................12

Table 5: Testbuilder Simulation Control................................................................................................13

Table 6: Simulation Options..................................................................................................................13

Table 7: MAC Configuration Options ....................................................................................................15

1 2 3 4 5 6 7 ... 17 18

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Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY Instrukcja Użytkownika Strona 2