Altera V-Series Avalon-MM DMA Instrukcja Użytkownika

V-Series Avalon-MM DMA Interface for PCIe SolutionsUser GuideLast updated for Altera Complete Design Suite: 14.1SubscribeSend FeedbackUG-011542014.12.

Compatibility Testing EnvironmentAltera has performed significant hardware testing to ensure a reliable solution. In addition, Alterainternally tests

Reset and Clocks62014.12.18UG-01154SubscribeSend FeedbackV-Series Hard IP for PCI Express IP Core includes both a soft reset controller and a hard res

Figure 6-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 6-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 6-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.ClocksThe Hard IP contains a clock domain c

The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.The transitions between Gen1, Gen2, and Gen3 should b

Link Width Max Link Rate Avalon Interface Width coreclkout_hip×4 Gen3 256 125 MHz×8 Gen3 256 250 MHzpld_clkcoreclkout_hip can drive the Application La

Error Handling72014.12.18UG-01154SubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can opti

Physical Layer ErrorsTable 7-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 7-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Table 1-6: Arria V Recommended Speed Grades for All Link Widths, Link Widths, and Application LayerClock FrequenciesLink Rate Link Width InterfaceWidt

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionReceiver overflow (1)Uncorrectable(fatal)This error occurs when a component receives a TLP thatviolates the FC credits allocate

The Hard IP block implements data poisoning, a mechanism for indicating that the data associated with atransaction is corrupted. Poisoned TLPs have th

Figure 7-1: Uncorrectable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that

IP Core Architecture82014.12.18UG-01154SubscribeSend FeedbackThe V-Series Avalon-MM Hard IP for PCI Express implements the complete PCI Express protoc

Figure 8-1: V-Series Avalon-MM DMA for PCI ExpressClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Hard IP for PCI ExpressDMA

Top-Level InterfacesAvalon-MM DMA InterfaceAn Avalon-MM interface with DMA connects the Application Layer and the Transaction Layer. Thisinterface inc

PIPEThe PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallelinterface to speed simulation; however, yo

Figure 8-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Link Rate Link Width InterfaceWidthApplication ClockFrequency (MHz)Recommended Speed GradesGen2x1 64 bits125–1, –2, –3, –4x2 64 bits 125 –1, –2, –3, –

Figure 8-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

Taking into account the overhead from TLP headers, this throughput is approximately 99% of themaximum theoretical performance.Using a 64-byte payload,

The following restrictions apply when you select the embedded the DMA Descriptor Controller:• BAR0 accesses the embedded DMA Descriptor Controller. BA

The DMA modules shown in the block diagrams implement the following functionality:• Read DMA –The Read DMA module sends memory read TLPs upstream and

Transceiver PHY IP Reconfiguration92014.12.18UG-01154SubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit performance is

Figure 9-1: Altera Transceiver Reconfiguration Controller ConnectivityThe following figure shows the connections between the Transceiver Reconfigurati

Figure 9-3: Specifying the Number of Transceiver Interfaces for Arria V GZ and Stratix V DevicesUG-011542014.12.18Connecting the Transceiver Reconfigu

Figure 9-4: Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V DevicesThe Transceiver Reconfiguration Controller includes an Op

Related Information• Altera Transceiver PHY IP Core User Guide• Application Note 645: Dynamic Reconfiguration of PMA Controls in Stratix V DevicesUG-0

Table 1-9: Stratix V Recommended Speed Grades for All Widths, Link Widths, and Application Layer ClockFrequenciesLink Rate Link Width InterfaceWidthAp

Transaction Layer Packet (TLP) Header FormatsA2014.12.18UG-01154SubscribeSend FeedbackThe following figures show the header format for TLPs without a

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-12: Configuration Write Request Root Port (Type 1)Configuration Write Request Root Port (Type 1)3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-15: Completion Locked with DataCompletion Locked with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1

Additional InformationB2014.12.18UG-01154SubscribeSend FeedbackRevision History for the Avalon-MM Interface with DMADate Version Changes Made2014.12.1

Date Version Changes Made2014.08.18 14.0 Arria 10Made the following changes to the V-Series Avalon-MM DMA forPCI Express IP core:• Revised programming

Date Version Changes MadeMade the following changes to the user guide:• Removed 125 MHz clock as optional refclk frequency in V-Series devices. V-Seri

Date Version Changes Made• Corrected the name of the Descriptor Instructions bus. The lettersDMA are now Ast. For example WrDMARXValid_i is nowWrAstRX

• Setting up and Running Analysis and SynthesisSteps in Creating a Design for PCI ExpressBefore you beginSelect the PCIe variant that best meets your

• Product Documentation• Non-Technical Suport (general)• LicensingTypographic ConventionsThe following table shows the typographic conventions this do

Visual Cue MeaningCourier typeIndicates signal, port, register, bit, block, andprimitive names. For example, data1, tdi, andinput. The suffix n denote

Visual Cue MeaningThe Feedback icon allows you to submit feedback to Altera about the document. Methods for collectingfeedback vary as appropriate for

Getting Started with the Avalon-MM DMA22014.12.18UG-01154SubscribeSend FeedbackYou can download the Qsys design example, pcie_de_ep_dma_g3x8_integrate

plan to replace the Descriptor Controller IP core with your own implementation, do not turn on theInstantiate internal descriptor controller in the pa

qsys-edit 3. Open pcie_de_ep_dma_g3x8_integrated.qsys.The following figure shows the Qsys system.Figure 2-1: V-Series Avalon-MM DMA for PCI Express Qs

Parameter ValuePath<working_dir>//pcie_de_ep_dma_g3x8_integrated6. Click Generate.Qsys generates the testbench.Understanding the Simulation Gene

The ld_debug command compiles all design files and elaborates the top-level design without anyoptimization.c. run -allThe simulation performs the foll

Datasheet12014.12.18UG-01154SubscribeSend FeedbackV-Series Avalon-MM DMA Interface for PCIe DatasheetAltera® V-Series FPGAs include a configurable, ha

8. On the Device page, choose the following target device family and options:a. In the Family list, select Stratix V (GS/GT/GX/E).b. In the Devices li

Figure 2-2: External Descriptor Controller ConnectivityUG-011542014.12.18Descriptor Controller Connectivity when Instantiated Separately2-7Getting Sta

Parameter Settings32014.12.18UG-01154SubscribeSend FeedbackSystem SettingsTable 3-1: System Settings for PCI ExpressParameter Value DescriptionNumber

Parameter Value Descriptionperformance forreceived requestsBalancedHighMaximumcredits, and completion data credits in the 16 KByte RX buffer.The 5 set

Parameter Value Description• Minimum RX Buffer credit allocation -performance forreceived requests )—configures the minimum PCIespecification allowed

Parameter Value DescriptionReference clockfrequency100 MHz125 MHzThe PCI Express Base Specification 3.0 requires a100 MHz ±300 ppm reference clock. Th

Parameter Value DescriptionUse ATX PLLOn/Off When you turn on this option, the Hard IP for PCI Expressuses the ATX PLL instead of the CMU PLL. For oth

Device Identification RegistersTable 3-3: Device ID RegistersThe following table lists the default values of the read-only Device ID registers. You ca

Device CapabilitiesTable 3-4: Capabilities RegistersParameter Possible Values Default Value DescriptionMaximumpayload size128 bytes256 bytes128 bytes

Link CapabilitiesTable 3-6: Link Capabilities Parameter Value DescriptionLink portnumber0x01 Sets the read-only value of the port number field in the

Table 1-1: PCI Express Data ThroughputThe following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8

Parameter Value DescriptionPending Bit Array(PBA) Offset[31:0] Used as an offset from the address contained in one of thefunction’s Base Address regis

Parameter Value DescriptionEndpoint L1acceptablelatencyMaximum of 1 usMaximum of 2 usMaximum of 4 usMaximum of 8 usMaximum of 16 usMaximum of 32 usNo

Interfaces and Signal Descriptions42014.12.18UG-01154SubscribeSend FeedbackThis chapter describes the top-level signals of V-Series the Avalon-MM DMA

Figure 4-1: Signals When Descriptor Controller Is Embedded in the Avalon-MM Bridgetx_out0[<n>-1:0]rx_in0[<n>-1:0]Hard IP SerialHard IP for

Figure 4-2: Signals When DMA Descriptor Controller Is Instantiated Externallytx_out0[<n>-1:0]rx_in0[<n>-1:0]Hard IP SerialHard IP for PCI

The Read DMA Avalon-MM Master Port interface performs two functions:• Provides the descriptor table to the Descriptor Controller: This module sends me

Write DMA Avalon-MM Master PortThe Write DMA module fetches data from the Avalon-MM address space using this interface beforeissuing memory write requ

If burst mode is not enabled, the RX Master module only supports 32-bit read or write request. All otherrequests received from the PCIe link are consi

Figure 4-5: RXM Master Writes To Memory in the Avalon-MM Address SpaceAvRxmAddress_<n>_o[63:0]AvRxmWrite_<n>_oAvRxmWriteData_<n>_o[3

Signal Name Direction DescriptionTxsWaitRequest_oOutput When asserted, indicates that the Avalon-MM slave port is notready to respond to a read or wri

• Extended credit allocation settings to better optimize the RX buffer space based on application type.• Optional end-to-end cyclic redundancy code (E

Signal Name DirectionDescriptionCraByteEnable_i[3:0]Input Byte enableCraWaitRequest_oOutput Wait request to hold off additional requestsCraChipSelect_

Avalon-ST Descriptor Status Interface when Instantiated SeparatelyWhen DMA module completes the processing for one Descriptor Instruction, it returns

Bits Name Description[153:146]DMA Descriptor IDSpecifies up to 128 descriptors.[159:154]Reserved—DMA Descriptor Status Bus when Instantiated Separatel

Signal Name Direction DescriptionRdDCMRead_oOutput When asserted, indicates a read transaction.RdDCMWaitRequest_iInput When asserted, indicates that t

Table 4-14: Read Descriptor Controller Avalon-MM Master InterfaceSignal Name Direction DescriptionRdDTSAddress_i[7:0]Input Specifies the descriptor ad

Clock SignalsTable 4-16: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified und

Table 4-17: Reset SignalsSignal Direction DescriptionnporInput Active low reset signal. In the Altera hardware example designs,npor is the OR of pin_p

Signal Direction Descriptioneven if the VVCCPGM of the bank is not 3.3V if the following 2conditions are met:• The input signal meets the VIH and VIL

Signal Direction Descriptionderr_cor_ext_rcv Output Indicates a corrected error in the RX buffer. This signal is fordebug only. It is not valid until

Signal Direction Descriptionint_status[3:0]Output These signals drive legacy interrupts to the Application Layer asfollows:• int_status[0]: interrupt

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVGen2 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 ×4, ×8×4, ×8Gen3 ×1, ×2,

Signal Direction Description• 00110: config.Linkwidthstart• 00111: Config.Linkaccept• 01000: Config.Lanenumaccept• 01001: Config.Lanenumwait• 01010: C

Signal Direction DescriptionNote that not all simulation models assert the Transaction Layererror bit in conjunction with the Data Link Layer error bi

Signal Direction DescriptionMSIControl_o[15:0]Output Provides system software control of the MSI messages as definedin Section 6.8.1.3 Message Control

for each PLL. The ×8 variants require an extra channel for PCS clock routing and control. The ×8 variantsuse channel 4 for clocking.Table 4-21: Number

Physical Layout of Hard IP In Arria V GX/GX/SX/ST DevicesArria V devices include one or two Hard IP for PCI Express IP cores. The following figures il

Figure 4-9: Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria SX DevicesCh5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch

Figure 4-10: Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria ST DevicesCh5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0Ch5Ch4Ch3Ch2Ch1Ch0C

Channel Placement in Arria V DevicesFigure 4-11: Arria V Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels shaded

Figure 4-12: Cyclone V GX/GT/ST/ST Devices with 9 or 12 Transceiver Channels and 2 PCIe CoresIn the following figure, the Hard IP for PCI Express uses

Channel Placement in Cyclone V DevicesFigure 4-14: Cyclone V Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels sh

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVTransactionLayer Packettype (TLP) • Memory ReadRequest• Mem

Figure 4-15: Physical Layout of Hard IP in Arria V GZ Devices6 Ch6 ChPCIeHardIPGXB_R2GXB_L2GXB_L1GXB_L0Ch5Ch4Ch3Ch2Ch1Ch06 Ch6 ChGXB_R1GXB_R024Channel

Figure 4-16: Stratix V GX/GT/GS Devices with Four PCIe Hard IP Blocks3 Ch6 Ch6 Ch6 Ch6 Ch6 Ch3 Ch6 Ch6 Ch6 Ch6 Ch6 ChPCIeHardIPPCIeHardIPPCIeHardIPIOB

Channel Placement in Arria V GZ and Stratix V GX/GT/GS DevicesFigure 4-17: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the

Figure 4-18: Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLsGen3 requires two PLLs to facilitate rate switching be

Figure 4-19: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLLSelecting the ATX PLL has the following advantages ove

Table 4-23: PIPE Interface SignalsIn the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulatio

Signal Direction Descriptionsim_pipe_ltssmstate0[4:0]Input andOutputLTSSM state: The LTSSM state machine encoding defines thefollowing states:• 5’b000

Signal Direction Descriptiontxcompl0 Output Transmit compliance <n>. This signal forces the runningdisparity to negative in compliance mode (neg

Test SignalsTable 4-24: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Related Information• PIPE Interface Signals on page 4-33• How can I observe the Hard IP for PCI Express PIPE interface signals for Arria V GZ and Stra

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVOut-of-ordercompletions(transparent tothe ApplicationLayer)

Registers52014.12.18UG-01154SubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 5-1: Corresponde

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x100:0x16C Virtual Channel Capability Structure(Reserved

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x008 Class Code, Revision ID Type 0 Configuration Space

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x034 Reserved, Capabilities PTR Type 0 Configuration Spa

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x818 Advanced Error Capabilities and ControlRegisterAdva

PCI Express Capability StructuresFigure 5-2: MSI Capability Structure0x0500x0540x058Message ControlConfiguration MSI Control Status Register Field Des

Figure 5-5: PCI Express AER Extended Capability StructureByte Offset 31:24 23:16 15:8 7:00x8000x804 Uncorrectable Error Status RegisterPCI Express Enh

Altera-Defined VSEC RegistersFigure 5-7: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 5-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 5-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Release InformationTable 1-3: Hard IP for PCI Express Release InformationItem DescriptionVersion 14.1Release Date December 2014Ordering Codes No order

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Bits Register Description Reset Value Access[0] Mask for the RX buffer uncorrectable ECC error. 1b’1 RWSUncorrectable Internal Error Status RegisterTa

Bits Register DescriptionResetValueAccess[1] When set, indicates a retry buffer uncorrectable ECC error.0RW1CS[0] When set, indicates a RX buffer unco

Bits Register Description Reset Value Access[5] When set, indicates a configuration error has been detected inCvP mode which is reported as correctabl

Figure 5-9: Block Diagram for External Descriptor ControllerAltera FPGAMemoryRead DMA Write DMA Hard IPfor PCIeRX MasterTX SlaveDMADescriptorControlle

1. Program the RD_DMA_LAST_PTR = 63.2. Program the RD_DMA_LAST_PTR = 127.3. Poll the status dword for read descriptor 63.4. Poll the status dword for

AddressOffsetRegister Access Description0x000CEP Read Descriptor FIFO Base(High)RW Specifies the upper 32 bits of the baseaddress of the read descript

AddressOffsetRegister Access Description0x0018RD_CONTROLRW[31:1] Reserved.[0]Done. When set, the DescriptorController writes the Done bit for eachdesc

AddressOffsetRegister Access Description0x010CEP Write Status and DescriptorFIFO Base (High)RW Specifies the upper 32 bits of the baseaddress of the w

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User GuideExample DesignsT

Read DMA and Write DMA Descriptor FormatRead and write descriptors are stored in separate descriptor tables. Each table can store up to 128 descrip‐to

AddressOffsetRegister NameDescription0x04WR_RC_HIGH_SRC_ADDRUpper dword of the write DMA source address.Specifies the address in the Avalon-MM domain

Figure 5-11: Descriptor Table FormatAssume the descriptor table includes 128 entries. The status table precedes a variable number ofdescriptors in mem

This is the upper 32 bits of the destination address.d. Program 0 to destination address 0xF000_0208.This is the lower 32 bits of the destination addr

Software Program for Simultaneous Read and Write DMAProgram the following steps to implement a simultaneous DMA transfer:1. Allocate Root Port memory

Control Register Access (CRA) Avalon-MM Slave PortTable 5-19: Configuration Space Register DescriptionsThe optional CRA Avalon-MM slave port provides

Byte OffsetRegister Dir Description14'h0018 cfg_sec_ctrl[15:0]O Secondary bus Control and Status register of thePCI-Express capability. This regi

Byte OffsetRegister Dir Description14'h0048 cfg_pr_lim_hi[43:32]O The upper 12 bits of the prefetchable limit registersof the Type1 Configuration

Byte OffsetRegister Dir Description14'h0064 ltssm_reg[4:0]OSpecifies the current LTSSM state. The LTSSM statemachine encoding defines the followi

Byte OffsetRegister Dir Description14'h006C lane_act_reg[3:0]O Lane Active Mode: This signal indicates the numberof lanes that configured during