Altera Stratix III Development Board Instrukcja Użytkownika Pobierz pdf (Strona 54)

2–46 Chapter 2: Board Components

Components and Interfaces

Stratix III 3SL150 Development Board May 2013 Altera Corporation

Reference Manual

J8 pin 43 Dedicated CMOS I/O bit 2

HSMB_D2

2.5 V AF32

J8 pin 44 Dedicated CMOS I/O bit 3

HSMB_D3

2.5 V AF31

J8 pin 47 LVDS TX or CMOS I/O bit 0

HSMB_TX_P0

LVDS or 2.5 V P11

J8 pin 48 LVDS RX or CMOS I/O bit 0

HSMB_RX_P0

LVDS or 2.5 V R4

J8 pin 49 LVDS TX or CMOS I/O bit 0

HSMB_TX_N0

LVDS or 2.5 V P10

J8 pin 50 LVDS RX or CMOS I/O bit 0

HSMB_RX_N0

LVDS or 2.5 V R3

J8 pin 53 LVDS TX or CMOS I/O bit 1

HSMB_TX_P1

LVDS or 2.5 V T9

J8 pin 54 LVDS RX or CMOS I/O bit 1

HSMB_RX_P1

LVDS or 2.5 V P4

J8 pin 55 LVDS TX or CMOS I/O bit 1

HSMB_TX_N1

LVDS or 2.5 V T8

J8 pin 56 LVDS RX or CMOS I/O bit 1

HSMB_RX_N1

LVDS or 2.5 V P3

J8 pin 59 LVDS TX or CMOS I/O bit 2

HSMB_TX_P2

LVDS or 2.5 V T7

J8 pin 60 LVDS RX or CMOS I/O bit 2

HSMB_RX_P2

LVDS or 2.5 V P2

J8 pin 61 LVDS TX or CMOS I/O bit 2

HSMB_TX_N2

LVDS or 2.5 V U6

J8 pin 62 LVDS RX or CMOS I/O bit 2

HSMB_RX_N2

LVDS or 2.5 V R1

J8 pin 65 LVDS TX or CMOS I/O bit 3

HSMB_TX_P3

LVDS or 2.5 V T5

J8 pin 66 LVDS RX or CMOS I/O bit 3

HSMB_RX_P3

LVDS or 2.5 V N2

J8 pin 67 LVDS TX or CMOS I/O bit 3

HSMB_TX_N3

LVDS or 2.5 V T4

J8 pin 68 LVDS RX or CMOS I/O bit 3

HSMB_RX_N3

LVDS or 2.5 V P1

J8 pin 71 LVDS TX or CMOS I/O bit 4

HSMB_TX_P4

LVDS or 2.5 V R10

J8 pin 72 LVDS RX or CMOS I/O bit 4

HSMB_RX_P4

LVDS or 2.5 V M1

J8 pin 73 LVDS TX or CMOS I/O bit 4

HSMB_TX_N4

LVDS or 2.5 V R9

J8 pin 74 LVDS RX or CMOS I/O bit 4

HSMB_RX_N4

LVDS or 2.5 V N1

J8 pin 77 LVDS TX or CMOS I/O bit 5

HSMB_TX_P5

LVDS or 2.5 V R7

J8 pin 78 LVDS RX or CMOS I/O bit 5

HSMB_RX_P5

LVDS or 2.5 V L2

J8 pin 79 LVDS TX or CMOS I/O bit 5

HSMB_TX_N5

LVDS or 2.5 V R6

J8 pin 80 LVDS RX or CMOS I/O bit 5

HSMB_RX_N5

LVDS or 2.5 V L1

J8 pin 83 LVDS TX or CMOS I/O bit 6

HSMB_TX_P6

LVDS or 2.5 V N9

J8 pin 84 LVDS RX or CMOS I/O bit 6

HSMB_RX_P6

LVDS or 2.5 V K4

J8 pin 85 LVDS TX or CMOS I/O bit 6

HSMB_TX_N6

LVDS or 2.5 V N8

J8 pin 86 LVDS RX or CMOS I/O bit 6

HSMB_RX_N6

LVDS or 2.5 V K3

J8 pin 89 LVDS TX or CMOS I/O bit 7

HSMB_TX_P7

LVDS or 2.5 V M7

J8 pin 90 LVDS RX or CMOS I/O bit 7

HSMB_RX_P7

LVDS or 2.5 V J4

J8 pin 91 LVDS TX or CMOS I/O bit 7

HSMB_TX_N7

LVDS or 2.5 V M6

J8 pin 92 LVDS RX or CMOS I/O bit 7

HSMB_RX_N7

LVDS or 2.5 V J3

J8 pin 95 LVDS or CMOS clock out

HSMB_CLK_OUT_P1

LVDS or 2.5 V P6

J8 pin 96 LVDS or CMOS clock in

HSMB_CLK_IN_P1

LVDS or 2.5 V N4

J8 pin 97 LVDS or CMOS clock out

HSMB_CLK_OUT_N1

LVDS or 2.5 V P5

J8 pin 98 LVDS or CMOS clock in

HSMB_CLK_IN_N1

LVDS or 2.5 V N3

J8 pin 101 LVDS TX or CMOS I/O bit 8

HSMB_TX_P8

LVDS or 2.5 V L7

Table 2–42. HSMC Port B Interface Signal Name, Description, and Type (Part 2 of 4)

Board

Reference

Description

Schematic

Signal Name

I/O Standard

Stratix III

Pin Number

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 81 82

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