Altera Stratix III Development Board Instrukcja Użytkownika Strona 62
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2–54 Chapter 2: Board Components
On-Board Memory
Stratix III 3SL150 Development Board May 2013 Altera Corporation
Reference Manual
Table 2–48 lists the DDR2 SDRAM devices A and B component reference and
manufacturing information.
Table 2–49 lists the DDR2 device B interface signals. JEDEC bus widths are used.
U17 pin D9 Data bit 5
DDR2_DEVA_DQ5
SSTL-18 class I U22-M24
U17 pin B1 Data bit 6
DDR2_DEVA_DQ6
SSTL-18 class I U22-H31
U17 pin B9 Data bit 7
DDR2_DEVA_DQ7
SSTL-18 class I U22-N25
U17 pin A8 Data strobe
DDR2_DEVA_DQS_N
SSTL-18 class I U22-C34
U17 pin B7 Data strobe
DDR2_DEVA_DQS_P
SSTL-18 class I U22-C33
U17 pin F8 Differential output clock
DDR2_DEVA_CK_N
SSTL-18 class I U22-K32
U17 pin E8 Differential output clock
DDR2_DEVA_CK_P
SSTL-18 class I U22-K31
U17 pin F2 Clock enable
DDR2_DEVA_CKE
SSTL-18 class I U22-M27
U17 pin G8 Chip select
DDR2_DEVA_CSn
SSTL-18 class I U22-E34
U17 pin F3 Write enable
DDR2_DEVA_WEn
SSTL-18 class I U22-G33
U17 pin G7 Column address strobe
DDR2_DEVA_CASn
SSTL-18 class I U22-G30
U17 pin F7 Row address strobe
DDR2_DEVA_RASn
SSTL-18 class I U22-F32
U17 pin B3 Data write mask
DDR2_DEVA_DM
SSTL-18 class I U22-F31
U17 pin F9 On-die termination control pin
DDR2_DEVA_ODT
SSTL-18 class I U22-M28
Table 2–47. DDR2 Device A Interface I/O (Part 2 of 2)
Board Reference Description
Schematic
Signal Name
I/O
Standard
Stratix III
Pin Number
Table 2–48. DDR2 SDRAM Devices A and B Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U17, U20
333 MHz devices for
32M ×8 (256 MBytes)
Micron Technology, Inc. MT47H32M8BP-3:B www.micron.com
Table 2–49. DDR2 Device B Interface I/O (Part 1 of 2)
Board Reference Description
Schematic
Signal Name
I/O
Standard
Stratix III
Pin Number
U20 pin H8 Address bit 0
DDR2_DEVB_A0
SSTL-18 class I U22-R27
U20 pin H3 Address bit 1
DDR2_DEVB_A1
SSTL-18 class I U22-R29
U20 pin H7 Address bit 2
DDR2_DEVB_A2
SSTL-18 class I U22-J31
U20 pin J2 Address bit 3
DDR2_DEVB_A3
SSTL-18 class I U22-U32
U20 pin J8 Address bit 4
DDR2_DEVB_A4
SSTL-18 class I U22-K34
U20 pin J3 Address bit 5
DDR2_DEVB_A5
SSTL-18 class I U22-T23
U20 pin J7 Address bit 6
DDR2_DEVB_A6
SSTL-18 class I U22-M34
U20 pin K2 Address bit 7
DDR2_DEVB_A7
SSTL-18 class I U22-U31
U20 pin K8 Address bit 8
DDR2_DEVB_A8
SSTL-18 class I U22-R24
U20 pin K3 Address bit 9
DDR2_DEVB_A9
SSTL-18 class I U22-V31
U20 pin H2 Address bit 10
DDR2_DEVB_A10
SSTL-18 class I U22-P34
U20 pin K7 Address bit 11
DDR2_DEVB_A11
SSTL-18 class I U22-T29
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- General Description 7
- Handling the Board 8
- 2. Board Components 9
- MSEL0 to GND 10
- Jumper (J13) 10
- Board Overview 11
- Featured FPGA (U22) 12
- Device Support 14
- I/O Resources 14
- MAX II CPLD 16
- FPGA Programming Over USB 25
- Notes to Table 2–7: 26
- Status Elements 27
- Board Specific LEDs 28
- Power Display 29
- JTAG Control DIP Switch 29
- Power Select Rotary Switch 31
- Clocking Circuitry 33
- Stratix III FPGA Clock Inputs 34
- General User Interfaces 36
- Note to Table 2–21: 37
- General User-Defined LEDs 38
- HSMC User-Defined LEDs 39
- User 7-Segment Display 40
- Power 7-Segment Display 41
- Character LCD 41
- Graphics LCD 43
- Radio at www.njr.co.jp 45
- Speaker Header 46
- Components and Interfaces 47
- High-Speed Mezzanine Cards 49
- On-Board Memory 56
- DDR2 SDRAM DIMM 57
- DDR2 SDRAM Devices 61
- QDRII+ SRAM 63
- Flash Memory 71
- Power Supply 75
- Power Measurement 76
- Notes to Table 2–60: 78
- Note to Table: 80
- Additional Information Info–3 81
- Typographic Conventions 81
- Info–4 Additional Information 82
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