Altera Transceiver PHY IP Core Instrukcja Użytkownika Pobierz pdf (Strona 179)

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Signal Name Direction Description

rx_parallel_data<n>

[67]

Output When asserted, indicates an RX FIFO overflow error.

rx_parallel_data<n>

[68]

Output When asserted, indicates that the RX FIFO is partially empty

and is still accepting data from the frame synchronizer. This

signal is asserted when the RX FIFO fill level is below the rx_

fifo_pempty threshold. This output is synchronous to the rx_

coreclkin clock domain. To prevent underflow, the Interlaken

MAC should begin reading from the RX FIFO when this signal

is deasserted, indicating sufficient FIFO contents (RX FIFO

level above rx_fifo_pempty threshold). The MAC should

continue to read the RX FIFO to prevent overflow as long as

this signal is not reasserted. You can assert a FIFO flush using

the rx_fifo_clr<n> when the receive FIFO overflows. This

output is synchronous to the rx_clkout clock domain.

Therefore, you must synchronize rx_parallel_data<n>[68]

to the rx_coreclkin before making the assignment below.

You can tie this signal's inverted logic to the rx_dataout_bp<n>

receive FIFO read enable signal as the following assignment

statement illustrates:

assign rx_dataout_bp[0] =!(rx_parallel_data[68]);

rx_parallel_data<n>

[69]

Output

When asserted, indicates that the RX FIFO has found the first

Interlaken synchronization word alignment pattern. For very

short metaframes, this signal may be asserted after the frame

synchronizer state machine validates frame synchronization

and asserts rx_parallel_data<n>[70] because this signal is

asserted by the RX FIFO which is the last PCS block in the RX

datapath. This output is synchronous to the rx_coreclkin

clock domain.

This signal is optional. If the RX PCS FIFO reaches the empty

state or is in an empty state, rx_parallel_data<n>[70]

indicating metaframe lock and rx_parallel_data<n>[69]

indicating that the first Interlaken synchronization word

alignment pattern has been received remain asserted, but rx_

parallel_data<n>[66] block lock and frame lock status signal

are deasserted in the next clock cycle.

7-12

Interlaken PHY Avalon-ST RX Interface

UG-01080

2015.01.19

Altera Corporation

Interlaken PHY IP Core

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