Altera Viterbi Compiler Instrukcja Użytkownika Pobierz pdf (Strona 38)

Figure 3-13: Output Timing - Example 2

With a different ending.

clk

source_sop

source_eop

source_rdy

source_val

decbit

Figure 3-14: Depuncturing Timing Diagram

This depuncturing timing diagram shows eras_sym for the pattern 110110 (puncturing rate 3/4). By

changing the eras_sym pattern you can implement virtually any depuncturing pattern you require.

clk

ena

val

sop

rr[8:5]

rr[4:1]

eras_sym[2]

eras_sym[1]

B X 7 A X 7

8 7 X D 9 X

3-20

Viterbi IP Core Timing Diagrams

UG-VITERBI

2014.12.15

Altera Corporation

Viterbi IP Core Functional Description

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Altera Viterbi Compiler Instrukcja Użytkownika Strona 38