Altera 100G Interlaken MegaCore Function Instrukcja Użytkownika Pobierz pdf (Strona 44)

supports your design in achieving timing closure more easily. In any case you must ensure that you hold

itx_num_valid at the value of 0 when you are not driving data.

You can think of this interface as a FIFO write interface. When itx_num_valid[7:4] is nonzero, both

data and control information (including itx_num_valid[7:4] itself) are written to the transmit side data

interface. The itx_ready signal is the inverse of a hypothetical FIFO-almost-full flag. When itx_ready is

high, the 100G Interlaken IP Core is ready to accept data. When itx_ready is low, you can continue to

send data for another 6 to 8 clock cycles of tx_usr_clk.

Related Information

100G Interlaken IP Core In-Band Calendar Bits on Transmit Side on page 4-17

Description of in-band calendar bits on the TX user data transfer interface.

4-14

100G Interlaken IP Core Back-Pressured Packet Transfer Example

UG-01128

2015.05.04

Altera Corporation

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Altera 100G Interlaken MegaCore Function Instrukcja Użytkownika Strona 44