Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika

40- and 100-Gbps Ethernet MAC and PHYMegaCore Function User GuideLast updated for Altera Complete Design Suite: 14.1SubscribeSend FeedbackUG-010882014

Simulation EnvironmentAltera performs the following tests on the 40-100GbE MAC and PHY IP core in the simulation environ‐ment using internal and third

Signal Name Descriptiontx_clk_ref In Sync–E variations (IP core duplex variations with the Sync–E optionenabled), this clock replaces clk_ref as the r

Figure 3-32: Clock Generation CircuitryProvides a high-level view of the clock generation circuitry and clock distribution to the transceiver. InSync–

Signal Name Direction Descriptionpcs_rx_arst_STInput PHY PCS RX asynchronous reset signalpcs_tx_arst_ST Input PHY PCS TX asynchronous reset signalpma_

Figure 3-33: Top-Level Signals of the 40-100GbE IP Core Without AdaptersEthernet Top-Level Signals without Adaptersrx_serial [<v>-1:0]tx_serial

Table 3-18: 40-100GbE MAC and PHY IP Core Without Adapters: Transmit Side SignalsSignal Name Direction Interfacemac_tx_arst_STInputResetspcs_tx_arst_S

Signal Name Direction Interfacetx_inc_64OutputStatistics counter incrementvectorstx_inc_127Outputtx_inc_255Outputtx_inc_511Outputtx_inc_1023Outputtx_i

Table 3-19: 40-100GbE MAC and PHY IP Core Without Adapters: Receive Side SignalsSignal Name Direction Descriptionmac_rx_arst_STInputResetspcs_rx_arst_

Signal Name Direction Descriptionremote_fault_from_rxOutputLink fault signaling interfaceThese two signals are not visiblein duplex variations.local_f

Signal Name Direction Descriptionrx_inc_runtOutputStatistics counter incrementvectorsrx_inc_64Outputrx_inc_127Outputrx_inc_255Outputrx_inc_511Outputrx

Table 3-20: 40-100GbE MAC and PHY IP Core Without Adapters: Common SignalsSignal Name Direction Descriptionpma_arst_STInput Resetsclk_refInput Clockst

Table 1-4: 40GbE IP Core FPGA Resource Utilization in Stratix V and Arria V GZ Devices Lists the resources and expected performance for selected varia

reconfig_to_xcvrInputExternal reconfigurationcontroller interfaceThese signals are available inArria V GZ and Stratix V devicesonly.The _to_xcvr<n&

upi_mode_en[3:0]Input40GBASE-KR4 microprocessorinterface. These signals arepresent only in 40GBASE-KR4variations for which you turn onEnable microproc

rc_busy[3:0]Input40GBASE-KR4 reconfigurationinterface. These signals arepresent only in 40GBASE-KR4variations for which you turn onEnable KR4 Reconfig

• 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface) on page 3-28• Control and Status Interface on page 3-51• External Reconf

Figure 3-34: Top-Level Signals of the 40-100GbE IP Core with AdaptersEthernet Top-Level Signals with AdaptersMAC and PHYAsynchronousReset SignalsAvalo

Signals of 40-100GbE MAC‑Only IP Core Variations40-100GbE MAC-only IP core variations are the variations that do not include a PHY. The signals in aMA

Figure 3-35: Top-Level Signals of the 40-100GbE IP Core with AdaptersEthernet Top-Level Signals with AdaptersMAC and PHYAsynchronousReset SignalsAvalo

Figure 3-36: Top-Level Signals of the 40-100GbE IP Core Without AdaptersEthernet Top-Level Signals without Adaptersrx_serial [<v>-1:0]tx_serial

The following 40-100GbE MAC and PHY IP core signals are not available in MAC-only IP corevariations:• Clock signals:• clk_ref (relevant only for IP co

Related Information• Lane to Lane Deskew Interface on page 3-43• Signals of MAC and PHY Variations Without Adapters on page 3-55• Signals of MAC and P

Module ALMs Logic RegistersMemoryM20K• alt_e40_mac_rx:mac_rx3000 7000 9• alt_e40_mac_tx:mac_tx2600 4800 0• alt_e40_mac_csr:mac_csr withoutstatistics c

Figure 3-37: Top-Level Signals of the 40-100GbE IP Core with AdaptersEthernet Top-Level Signals with AdaptersMAC and PHYAsynchronousReset SignalsAvalo

Figure 3-38: Top-Level Signals of the 40-100GbE IP Core Without AdaptersEthernet Top-Level Signals without Adaptersrx_serial [<v>-1:0]tx_serial

The following 40-100GbE MAC and PHY IP core signals are available in PHY-only IP core variations:• Clock signals:• clk_ref (relevant only for IP core

• Lane to Lane Deskew Interface on page 3-43Describes the lanes_deskewed PHY output signal.• MAC to PHY Connection Interface on page 3-43• External Re

Word Offset Register Description0x01A Test pattern counter register.0x01B One of two link fault signaling registers.0x01C Reserved.0x01D PHY reset reg

Word Offset Register Description0x118–0x11F Reserved.0x120 MAC hardware error register.0x121 MAC reset register.0x122 One of two link fault signaling

Table 3-25: 40-100GbE Example Design RegistersLists the memory mapped registers for the 40-100GbE IP core example design.Word Offset Register Category

Lock Status Registers on page 3-84Bit Error Flag Registers on page 3-86PCS Hardware Error Register on page 3-87BER Monitor Register on page 3-87Test M

Table 3-26: Scratch and Clock Registers for Applicable DevicesAddress Name ApplicableDevice(s)Bit Description HW ResetValueAccess0x000PHY_VERSIONArria

Address Name ApplicableDevice(s)Bit Description HW ResetValueAccess0x007 GX_CTRL1 Stratix IV[31] When set, places thetransceiver in Internalserial loo

Module ALMs Logic RegistersMemoryM20K40GBASE-KR4 PHY• AN• LT• FEC• Use M20K blocksfor FEC buffer23800 24500 840GBASE-KR4 PHY• AN• LT• FEC• Do not use

Table 3-27: Stratix IV Transceiver Analog Settings Register GX_CTRL1—Offset 0x007—Bits [28:4]Describes the fields in bits [28:4] of the analog setting

Lock Status RegistersThe following registers show the lock status of the high speed I/O and RX PCS. RX_AGGREGATE[0]aggregates the status of the indivi

Address Name Bit Description HW ResetValueAccess0x010IO_LOCKS For theCAUI-4 configu‐ration only .[31:26] Reserved. 0x3f R[25:22] When asserted, indica

Address Name Bit Description HW ResetValueAccess0x014 RX_AGGREGATE[4] When asserted, indicates a change inPCS-VLANE permutation. This statusbit clears

PCS Hardware Error RegisterTable 3-30: PCS Hardware Error RegisterAddress Name Bit Description HWResetValueAccess0x017 PCS_HW_ERR[8] When asserted, in

Test Mode RegisterTable 3-32: Test Mode Register—Offset 0x019Address Name Bit Description HWResetValueAccess0x019 TEST_MODE[2] This bit clears the tes

Table 3-35: Link Fault Signaling Configuration Register—Offset 0x122Address Name Bit Description HWResetValueAccess0x122MAC/RS linkfaultsequenceconfig

Table 3-36: MAC Reset RegisterWriting a 1’b1 to any of the reset register fields initiates the corresponding reset sequence.Address Name Bit Descripti

PCS‑VLANE RegistersTable 3-38: PCS‑VLANE RegistersWhen the RX PCS is properly locked, the PCS-VLANE registers contain a permutation of the numbers [0–

Address Name Bit Description HWResetValueAccess0x023 PCS VLANE3[9:5] Virtual index for physical lane 19 5h’00 R[4:0] Virtual index for physical lane 1

Module ALMs Logic RegistersMemoryM9KMAC with Avalon-STclient interface andwith statisticscounters13700 22200 20• alt_e40_adapter_rx:adapter_rx700 1000

Table 3-40: 40-100GbE IP Core 40GBASE-KR4 Registers and Register Fields Not in 10GBASE-KR PHY IP CoreDocuments the differences between the 10GBASE-KR

Address Name Bit Description HWResetValueAccess0x0B9KR4 FECCorrectedBlocks, Lane2[31:0]Maintains count of corrected FEC blocks onLane 2, saturating (n

Address Name Bit Description HWResetValueAccess0x0CCOverride ANChannelSelect[3:0]If you set the value of the Override AN ChannelEnable register field

Address Name Bit Description HWResetValueAccess0x0D1Updated TXCoef new,Lane 1[5]When set to 1, indicates that new link partnercoefficients are availab

Address Name Bit Description HWResetValueAccess0x0D1Updated RXCoef new,Lane 1[9]When set to 1, indicates that new local devicecoefficients are availab

Address Name Bit Description HWResetValueAccess0xD2[15:8]Register bits 0xD2[7:0] refer to Lane 0. These bitsare the equivalent of 0xD2[7:0] for Lane 1

Address Name Bit Description HWResetValueAccess0xE6 This register is the equivalent of register 0xD5 for Lane 2 link training. (Refer to 10GBASE-KR PH

Address Name Bit Description HW ResetValueAccess0x102MAC_CMD_config[4] When set to 1, the transmit CRC FIFO iscleared. Used for hardware diagnostics.

Address Name Bit Description HW ResetValueAccess0x103RX_FILTER_CTRL[17:8]Packet length limit in 16-byte words, for the40GbE IP core. The IP core disca

Related Information• 40-100GbE IP Core RX Filtering on page 3-21Describes how the IP core interprets the packet length limits in RX_FILTER_CTRL[17:8]

Module ALMs Logic RegistersMemoryM9K• • alt_e40_pcs_tx:pcs_tx3600 3900 0• • alt_e40_phy_csr:phy_csr700 1100 0• alt_e40_phy_pma_siv:pma600 500 0Related

Addr Name Bit Description HW ResetValueAccess0x113RECEIVE_PAUSE_CONTROL[9] When set to 1, enables unicast pause receive. 1’b0 RW[8] When set to 1, ena

MAC Hardware Error RegisterTable 3-43: MAC Hardware Error RegisterAddress Name Bit Description HWResetValueAccess0x120 MAC_HW_ERR[6] When asserted, in

CRC Configuration RegisterTable 3-44: CRC Configuration RegisterAddress Name Bit Description HWResetValueAccess0x123 CRC_CONFIG[1] The RX CRC configur

Address Name Bit Description HWResetValueAccess0x125PreamblePass-ThroughConfiguration[1] Enable TX preamble pass-through. This bit has thefollowing va

• 40-100GbE IP Core Preamble Processing on page 3-21Describes the RX preamble pass-through feature and the effect of bit [0] of the Preamble Pass-Thro

Address Name Bit Description HW ResetValueAccess0x160 DST_AD0_LO [23:0] Destination address 0 (lower 24 bits). 0x00000000 RW0x161 DST_AD0_HI [23:0] De

parameter in the 40-100GbE parameter editor, the counters are not implemented in the CSR, and readaccess to the counters returns read data equal to 0.

Address Name- Description Access0x20C CNTR_TX_1519toMAXB_LONumber of transmitted frames between 1519 and max sizedefined in 0x103 (lower 32 bits)RO0x2

Address Name- Description Access0x21C CNTR_TX_MCAST_CTRL_LONumber of valid multicast frames transmitted (lower 32bits)RO0x21D CNTR_TX_MCAST_CTRL_HINum

Address Name- Description Access0x22B CNTR_TX_ST_HI Number of transmitted frame starts, excluding pause frames(upper 32 bits)RO0x22C CNTR_TX_DB_LO Num

Module ALMs Logic RegistersMemoryM20KMAC with Avalon-STclient interfacewithout statisticscounters21600 45200 28MAC with Avalon-STclient interface andw

Address Name- Description Access0x28A CNTR_RX_1024to1518B_LONumber of received frames between 1024–1518 bytes (lower32 bits)RO0x28B CNTR_RX_1024to1518

Address Name- Description Access0x29A CNTR_RX_UCAST_DATA_OK_LONumber of valid unicast frames received, excluding controlframes (lower 32 bits)RO0x29B

Address Name- Description Access0x2A9 CNTR_RX_CRCERR_HINumber of received frames between the length of 64 and thevalue configured in 0x103 register wi

Address Name- Description Access0x2B7 Reserved0x2B8 CNTR_RX_FCS Number of received packets with FCS errors. This registermaintains a count of the numb

Address Name Bits Description HW Reset Value Access0x403 CMD_STATUS[6] PMD global alarm. 1b’0 R[5] Programmable alarm 3. Defaults tomodule ready.1b’0

Address Name Bits Description HW Reset Value Access0x411 MDIO_RDATA[31] Link is busy. 1b’0 R[15:0] Result of previous read. 0x0000 R0x412 MDIO_ADDR[14

Address Name Bits Description HW Reset Value Access0x421 2WS_RDATA[31] When asserted, the link is busy. 1b’0 R[30] When asserted, indicates that thesl

Term DefinitionFCS Frame Check Sequence. A CRC-32 with bit reordering and inversion.Frame Ethernet formatted packet. A frame consists of a start delim

Debugging the 40GbE and 100GbE Link42014.12.15UG-01088SubscribeSend FeedbackIf you are experiencing difficulties bringing up your 40-100GbE IP core li

40-100GbE IP Core Example DesignA2014.12.15UG-01088SubscribeSend FeedbackAltera provides an example design with the 40-100GbE IP core. This example de

Module ALMs Logic RegistersMemoryM20K• alt_e100_phy_pcs:phy_pcs23000 41700 0• • alt_e100_pcs_rx:pcs_rx13600 26300 0• • alt_e100_pcs_tx:pcs_tx8700 1370

Figure A-1: High Level Block Diagram for the 40-100GbE Example DesignHigh level block diagram for non-40GBASE-KR4 example designs. You can generate a

Figure A-2: High Level Block Diagram for the 40GBASE-KR4 Example DesignHigh level block diagram for 40GBASE-KR4 example designs. You can generate a 40

The interface between the MAC and PHY modules of the IP core is XLGMII for the 40GbE IP core andCGMII for the 100GbE IP core. The interface between th

Address Map Changes for the 40-100GbE IPCore v12.0 ReleaseB2014.12.15UG-01088SubscribeSend FeedbackTable B-1: Address Map and Register Name Changes fo

10GBASE-KR RegistersC2014.12.15UG-01088SubscribeSend FeedbackThis appendix duplicates the 10GBASE-KR PHY register listings from the Altera Transceiver

The following table specifies the control and status registers that you can access over the Avalon-MMPHY management interface. A single address space

WordAddrBit R/W Name Description18 RW Assert KR FECRequestWhen set to 1, indicates that the core is requesting the FECability. When this bit changes,

WordAddrBit R/W Name Description0xB4 31:0 RSC FEC UncorrectedBlocksCounts the number of uncorrectable FEC blocks. Resets to 0when read. Otherwise, it

WordAddrBit R/W Name Description3 RO AN ADV RemoteFaultWhen set to 1, fault information has been sent to the linkpartner. When 0, a fault has not occu

WordAddrBit R/W Name Description• [4:0]: Selector• [9:5]: Echoed nonce which are set by the state machine• [12:10]: Pause bits• [13]: Remote Fault bit

Module ALMs Logic RegistersMemoryM9KMAC with Avalon-STclient interface andwith statisticscounters35600 55000 29• alt_e100_adapter_rx:adapter_rx4100 63

WordAddrBit R/W Name Description0xC5 15:0 RW User Next pagelowThe Auto-Negotiation TX state machine uses these bits if theAuto-Negotiation next pages

WordAddrBit R/W Name Description0xCB24:0RO AN LP ADV Tech_A[24:0]Received technology ability field bits of Clause 73Auto-Negotiation. The 10GBASE-KR P

WordAddrBit R/W Name Description7:4 RW main_step_cnt[3:0]Specifies the number of equalization steps for each main tapupdate. There are about 20 settin

WordAddrBit R/W Name Description22:20 RW rx_ctle_modeRX CTLE mode in the Link Training algorithm. The defaultvalue is 3'b000. The following encod

WordAddrBit R/W Name Description0xD20RO Link Trained -Receiver statusWhen set to 1, the receiver is trained and is ready to receivedata. When set to 0

WordAddrBit R/W Name Description19:10 RW ber_time_k_frames Specifies the number of thousands of training frames toexamine for bit errors on the link f

WordAddrBit R/W Name Description13:8 RO LD coefficientstatus[5:0]Status report register for the contents of the second, 16-bitword of the training fra

WordAddrBit R/W Name Description23 ROorRWLP PresetCoefficientsWhen set to 1, The local device TX coefficients are set to astate where equalization is

WordAddrBit R/W Name Description0xD55:0 R LT VOD setting Stores the most recent VOD setting that LT specified using theTransceiver Reconfiguration Con

WordAddrBit R/W Name Description20:16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter. Whenenabled, this value substitutes for the VPOSTRU

Module ALMs Logic RegistersMemoryM9K• • alt_e100_pcs_tx:pcs_tx11200 16600 0• • alt_e100_phy_csr:phy_csr1100 1700 0• alt_e100_phy_pma_siv:pma600 500 0I

Additional InformationD2014.12.15UG-01088SubscribeSend Feedback40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User GuideRevision HistoryTable

Date ACDSVersionChanges• Added link to Low Latency 40-100GbE IP core user guide in About the40- and 100-Gbps Ethernet MAC and PHY MegaCore Function an

Date ACDSVersionChanges• In "Simulating the 40-100GbE IP Core with the Testbenches" section,removed option to include or exclude waveform ge

Date ACDSVersionChangesJune 2013 1.3(v13.0softwarerelease)• Updated for use with version 13.0 of the Quartus II software and theMegaWizard Plug-In Man

Date ACDSVersionChangesDecember20121.2 • Updated Slowest Supported Device Speed Grades table on page 1–4:• Supported speed grades for the Arria V GZ d

Date ACDSVersionChanges• If you are transitioning from an earlier version of the IP core, you mustcomplete the following steps:• Generate the 12.1 rel

June 2012 1.0 • Updated for use with version 12.0 of the Quartus II software.• Updated address map.• Updated device family support.• Updated interface

November2011EarlyAccess• Corrected the following issues in the MegaCore function:• Corrected sequence ordered set encoding in PCS.• Corrected error co

How to Contact AlteraTable D-2: How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to this table. You can als

Visual Cue MeaningItalic Type with Initial Capital Letters Indicate document titles. For example, Stratix VDesign Guidelines.italic type Indicates va

ContentsAbout the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function...1-140- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features...

Module ALMs Logic RegistersMemoryM20KMAC&PHY withAvalon-ST clientinterface and withstatistics counters54600 110100 28MAC with Avalon-STclient inte

Module ALMs Logic RegistersMemoryM20K• alt_e100_mac_csr:mac_csr withstatistics counters4600 8500 0PHY 28600 57400 0• alt_e100_phy_pcs_caui4:phy_pcs272

Item DescriptionOrdering Codes IP-40GEMACIP-40GEPHYIP-100GEMACIP-100GEPHYIP-40GEMACPHYIP-100GEMACPHYIP-40GBASEKR4PHYProduct ID 40Gb Ethernet MAC: 00DF

Getting Started22014.12.15UG-01088SubscribeSend FeedbackThe following sections explain how to install, parameterize, simulate, and initialize the 40-1

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for production use without purchasing anadditional licen

Specifying the 40-100GbE IP Core Parameters and OptionsThe 40-100GbE parameter editor allows you to quickly configure your custom IP variation. Use th

Parameter Type Range Default Setting Parameter DescriptionMAC configu‐rationString • 40 GbE• 100 GbE100 GbE Selects the MAC datapath width.Core option

Parameter Type Range Default Setting Parameter DescriptionPHY referencefrequency (2)Integer(encoding)The range and default settings dependon the PHY c

Table 2-2: 40-100GbE Parameters: 40GBASE-KR4 TabDescribes the parameters for customizing a 40GBASE-KR4 40-100GbE IP core, on the 40GBASE-KR4 tab of th

Parameter Type Range DefaultSettingParameter DescriptionAuto-Negotia‐tion MasterString • Lane 0• Lane 1• Lane 2• Lane 3Lane 0 Selects the master chann

40-100GbE IP Core TX Datapath...3-340-100GbE IP Core TX

Parameter Type Range DefaultSettingParameter DescriptionINITPREVAL Integer0–15 5Specifies the initial Pre-tap value.Link Training: GeneralEnable LinkT

Parameter Type Range DefaultSettingParameter DescriptionInclude FECsublayerBoolean • True• FalseFalse If this parameter is turned on, the IP core incl

• 40-100GbE IP Core Testbenches on page 2-14Provides a list of IP core variations (parameter value choices) for which the Quartus II software cangener

In the top-level wrapper file for your simulation project, you can set the FAST_SIMULATION parameter toenable simulation optimization. Parameters are

You can use the IP Catalog to generate an Altera transceiver reconfiguration controller.• For Arria V GZ and Stratix V devices, select the Transceiver

Table 2-5: External Altera Transceiver Reconfiguration Controller Ports for Connection to 40-100GbE IPCore Signal Name Direction Descriptionreconfig_t

• ALTGX_RECONFIG Megafunction User Guide for Stratix IV DevicesChapter in volume 3: Transceiver Configuration Guide of the Stratix IV Device Handbook.

custom streaming client interface) are identical, except for the bandwidth. The following sections firstdescribe the testbenches that include adapters

Figure 2-4: 40GBASE-KR4 40GbE IP Core Testbench with AdaptersIllustrates the top-level modules of the 40GBASE-KR4 example testbench that uses adapters

File Names Descriptionrun_vcs.shThe Synopsys VCS script to run the testbench.run_ncsim.shThe Cadence NCSim script to run the testbench.Figure 2-5: Typ

About the 40- and 100-Gbps Ethernet MAC andPHY MegaCore Function12014.12.15UG-01088SubscribeSend FeedbackThe Altera® 40- and 100-Gbps Ethernet (40GbE

7. At marker 7, the 40GbE IP core asserts l4_rx_valid, indicating that the it has valid data to send to theclient on l4_rx_data[255:0].8. At marker 8,

File Names Descriptionalt_40gbe_tb.sv, alt_100gbe_tb.v The testbench wrapper file.Testbench Scriptsrun_vsim.doThe ModelSim script to run the testbench

Simulating the 40‑100GbE IP Core With the TestbenchesYou can simulate the 40-100GbE IP core using the Altera-supported versions of the Mentor Graphics

Generating the 40-100GbE TestbenchA single procedure generates both the testbench and the example project. To generate the testbench andexample projec

The successful testbench run displays the following output:# # *****************************************# ** 40g Ethernet Testbench# **# **# ** Ta

Testbench Output Example: 100GbE IP Core with AdaptersThis section shows successful simulation using the 100GbE IP core with adapters testbench (alt_1

# ** Sending Packet 5...# ** Sending Packet 6...# ** Sending Packet 7...# ** Sending Packet 8...# ** Sending P

• Control and Status Interface on page 3-51In step 3, write to the MAC_CMD_config register using this interface.• MAC Configuration and Filter Registe

Functional Description32014.12.15UG-01088SubscribeSend FeedbackThis chapter provides a detailed description of the 40-100GbE IP core. The chapter begi

High Level System OverviewFigure 3-1: 40GbE and 100GbE MAC and PHY MegaCore FunctionMain block, internal connections, and external block requirements.

Figure 1-1: 40GbE and 100GbE MAC and PHY MegaCore FunctionMain block, internal connections, and external block requirements.40- or 100-Gbps Ethernet M

The MAC includes the following interfaces:• Datapath client-interface–The following options are available:• 40GbE with adapters—Avalon-ST, 256 bits• 4

Figure 3-2: Typical Client Frame at the Transmit InterfaceIllustrates the changes that the TX MAC makes to the client frame. This figure uses the foll

Related InformationMAC Address Registers on page 3-107Includes information about the MADDR_CTRL, SRC_AD_LO, and SRC_AD_HI registers.Length/Type Field

Related InformationMAC Feature Configuration Registers on page 3-105Includes information about the IPG_DEL_PERIOD and IPG_DEL_ENABLE registers.40-100G

bits). In both cases the client interfaces operate at a frequency above 315 MHz in the standard IP corevariations, and at or above the frequency of 19

Signal Name Direction Descriptionl<n>_tx_readyOutput When asserted, the MAC is ready to receive data. Thel<n>_tx_ready signal acts as an a

Figure 3-5: Traffic on the TX and RX Client Interface for 100GbE IP Core Using the Eight- to Five-WordAdaptersShows typical traffic for the TX and RX

Table 3-3: Signals of the TX Client Interface Without AdaptersIn the table, <w> = 2 for the 40GbE IP core and <w> = 5 for the 100GbE IP co

Figure 3-7: Reduced Bandwidth With Left-Aligned SOP RequirementIllustrates the reduction of bandwidth that would be caused by left-aligning the SOP fo

40GbE IP Core Without AdaptersThe following figures illustrate the transmission of a short packet when preamble pass-through is turnedoff and when it

40- and 100-Gbps Ethernet MAC and PHY IP Core Supported FeaturesThe 40- and 100-Gbps Ethernet MAC and PHY IP core offers the following features:• Para

Figure 3-9: Short Packet Example With PreambleIllustrates the transmission of a short packet when preamble pass-through is turned on. In this example,

Figure 3-10: Sample 40GbE IP Core TX Bus ActivityIllustrates the deassertion of the din_ack signal. The data beginning with 0xe6e7 is not immediatelya

Figure 3-12: Short TX Packet Example With PreambleIllustrates the transmission of a short packet for the 100GbE IP core when preamble pass-through ist

For example, din_start might be set to 5’b11000, indicating the start of a new packet in two successivewords. In this case, din_end_pos could equal 40

Figure 3-15: Octet Transmission on the Avalon-ST Signals Without Preamble Pass-ThroughIllustrates how the octets of the client frame are transferred o

Figure 3-16: Byte Order on the Avalon-ST Interface Lanes With Preamble Pass‑ThroughDescribes the byte order on the Avalon-ST interface when the preamb

Figure 3-17: Octet Transmission on the Avalon-ST Signals With Preamble Pass-ThroughIllustrates how the octets of the client frame are transferred over

40-100GbE IP Core RX DatapathThe 40-100GbE RX MAC receives Ethernet frames from the PHY and forwards the payload with relevantheader bytes to the clie

40-100GbE IP Core RX FilteringThe 40-100GbE IP core can operate in cut-through mode or in store and forward mode. In cut-throughmode, the IP core does

By default, the MAC RX removes all Start, SFD, preamble, and IPG bytes from accepted frames. However,if you turn on the RX preamble pass-through featu

• Programmable IPG fine adjustment for Ethernet repeater/bump-in-the-wire applications and trafficshaping.• Ethernet flow control using the pause regi

Figure 3-20: Flow of Frame Through the MAC RX Without Preamble Pass-ThroughIllustrates the typical flow of frame through the MAC RX when the preamble

Related InformationMAC Feature Configuration Registers on page 3-105Information about the PAD_CONFIG register.Address CheckingThe RX MAC supports all

• Pause Registers on page 3-10240-100GbE IP Core RX Data Bus InterfacesThis section describes the RX data bus at the user interface and includes the f

Figure 3-22: RX MAC to Client Interface with AdaptersThe Avalon-ST interface bus width varies with the IP core variation. In the figure, <n> = 4

Figure 3-23: Traffic on the TX and RX Client Interface for 40GbE IP Core Using the Four- to Two-WordAdaptersShows typical traffic for the TX and RX Av

40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)The RX bus without adapters consists of five 8-byte words, or 320 bits, ope

Signal Name Direction Descriptiondout_runt_last_data[<w>-1:0]Output Indicates that the last_data (the final data byte of the frame) is the final

100GbE IP Core RX Client Interface ExamplesExample on RX Client Interface Without Preamble Pass-ThroughFigure 3-26: Typical Traffic on the RX Client I

The dout_payload signal marks words that contain frame data payload. Words that contain data payloadmight also contain Idle or sequence control inform

Error Conditions on the RX DatapathThe RX MAC indicates error conditions by asserting l<n>_rx_error. The following error conditions aredefined:•

Device Support Level DefinitionFinal The IP core is verified with final timing models forthis device family. The IP core meets all functionaland timin

Congestion and Flow Control Using Pause FramesThe 40-100GbE IP core provides flow control to reduce congestion at the local or remote link partner.Whe

Conditions Triggering XOFF Frame TransmissionThe TX MAC transmits XOFF frames when one of the following conditions occurs:• Client requests XOFF trans

Pause Transmission LogicFigure 3-29: Block Diagram of the Pause Transmission Logic Tx MACMac Data and ControlFrame Generator Rx MACFrame ProcessorXOFF

Signal Name Direction Descriptionpause_insert_mcast Input When asserted, specifies that the IP core should generate a pausepacket with the well-known

packet filtering. The reset state for both bits is 1, where filtering is enabled. The bits are gated byRX_FILTER_CTRL bit [0], which enables and disab

MAC and the XLGMII or CGMII to manage local and remote faults. Link fault signaling on the Ethernetlink is disabled by default but can be enabled by t

Signal Name Direction Descriptionlocal_fault_statusOutputAsserted when local fault is detected in RX MAC in a duplex IPcore variation. In duplex IP co

Name SignalDirectionDescriptiontx_inc_mcast_data_errOutput Asserted for one cycle when an errored multicast TX frame, excludingcontrol frames, is tran

Name SignalDirectionDescriptionrx_inc_127Output Asserted for one cycle when a 65–127 byte RX frame is received.rx_inc_255Output Asserted for one cycle

Name SignalDirectionDescriptionrx_inc_fcs_errOutput Asserted for one cycle when a RX packet with FCS errors is received.Assertion of this signal might

MegaCore Function Device Family Supported Speed Grades40GbE (24.24 Gbps option)Arria V GZ I3, C3Stratix IV (GX) I3, C3Stratix IV (GT) I3Stratix V (GX)

Control Data Description1 fd End of Frame (fd = frame done).1 fe XL/CGMII Error. Typically a bit error which switched a 66-bit blockbetween data and c

Table 3-12: Lane to Lane Deskew Interface SignalsSignal Name Direction Descriptionlanes_deskewedInput Indicates lane to lane skew iscorrected. Availab

align_status is true and the scrambled idle RX test-pattern mode is active, the scrambled idle test-pattern checker observes the synchronous header an

40GBASE-KR4 IP Core VariationsThe 40GBASE-KR4 IP core supports low-level control of analog transceiver properties for link trainingand auto-negotiatio

Related InformationAltera Transceiver PHY IP Core User GuideThe 40GBASE-KR4 variations of the 40-100GbE IP core use the Altera 10GBASE-KR PHY IP core.

Signal Name Direction Descriptiontap_to_upd[11:0]Output Specifies the TX equalization tap to update to optimizesignal quality. Each lane's field

Signal Name Direction Descriptionpcs_mode_rc[5:0]Output Specifies the PCS mode for reconfiguration. Has thefollowing valid values:• b'000001: aut

Signal Name Direction Descriptionupi_adj[7:0]Input Selects the active tap for the corresponding lane. Each lane'sfield has the following valid va

Signal Name Direction Descriptionupo_ber_max[3:0]Output When a bit is asserted, the BER counter for thecorresponding lane has rolled over.upo_coef_max

to 644.53125 MHz ±100 ppm. For 24.24 Gbps variations, you must set the frequency of clk_ref either to390.625 MHz ±100 ppm or to 195.3125 MHz ±100 ppm.