Altera 50G Interlaken MegaCore Function Instrukcja Użytkownika Strona 63
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50G Interlaken IP Core Register Map
6
2015.05.04
UG-01140
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The 50G Interlaken IP core control registers are 32 bits wide and are accessible to you using the
management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.
This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 6-1: 50G Interlaken IP Core Register Map
Offset Name R/W Description
9'h0
PCS_BASE
RO [31:8] – Constant “HSi” ASCII
[7:0] – version number
Despite its name, this register does not encode the hard PCS
base address.
9'h1
LANE_COUNT
RO Number of lanes
9'h2 TEMP_SENSE RO Device temperature according to the internal temperature
sensing diode.
[7:0] – the temperature in degrees Fahrenheit
[15:8] – the temperature in degrees Celsius
For example, when the temperature is 54 degrees Celsius
(130 degrees Fahrenheit), the value of the register is 0x3682.
To interpret this register value, you read 0x36 (decimal 54)
to be the temperature in degrees Celsius, and you read 0x82
(decimal 130) to be the temperature in degrees Fahrenheit.
This register is invalid in the following IP core variations:
• Variations that target an Arria 10 device
• Variations in which you turn off the hidden parameter
Include Temp Sense
9'h3 ELAPSED_SEC RO [23:0] - Elapsed seconds since power up. The IP core
calculates this value from the management interface clock
(mm_clk) for diagnostic purposes. During continuous
operation, this value rolls over every 194 days.
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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