Altera Arria 10 Avalon-MM DMA Instrukcja Użytkownika Strona 1

Arria 10 Avalon-MM DMA Interface forPCIe SolutionsUser GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-01145_avmm_dma

Transaction LayerPacket type (TLP)(transmit support)Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVCompletion-Lock

Arria 10 Reset and Clocks72015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackFigure 7-1: Reset Controller in Arria 10 DevicesExample Designaltpcied_<

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 7-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 7-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.ClocksThe Hard IP contains a clock domain c

As this figure indicates, the IP core includes the following clock domains:coreclkout_hipTable 7-1: Application Layer Clock Frequency for All Combinat

Name Frequency Clock Domainrefclk 100 MHz SERDES (transceiver). Dedicated free running inputclock to the SERDES block.7-6Clock SummaryUG-01145_avmm_dm

Error Handling82015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and

Physical Layer ErrorsTable 8-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 8-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Device Family SupportTable 1-5: Device Family SupportDevice Family SupportArria 10Preliminary. The IP core is verified with prelimi‐nary timing models

Error Type DescriptionReceiver overflow (1)Uncorrectable(fatal)This error occurs when a component receives a TLP thatviolates the FC credits allocate

The Hard IP block implements data poisoning, a mechanism for indicating that the data associated with atransaction is corrupted. Poisoned TLPs have th

Figure 8-1: Uncorrectable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that

IP Core Architecture92015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackThe Arria 10 Avalon-MM Hard IP for PCI Express implements the complete PCI Expre

Figure 9-1: Arria 10 Avalon-MM DMA for PCI ExpressClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Hard IP for PCI ExpressDMA

Top-Level InterfacesAvalon-MM DMA InterfaceAn Avalon-MM interface with DMA connects the Application Layer and the Transaction Layer. Thisinterface inc

• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalizat

Figure 9-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 9-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

models (BFMs) driving the PCI Express link interface. Altera performs the following tests in thesimulation environment:• Directed and pseudorandom sti

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

Taking into account the overhead from TLP headers, this throughput is approximately 99% of themaximum theoretical performance.Using a 64-byte payload,

The following restrictions apply when you select the embedded the DMA Descriptor Controller:• BAR0 accesses the embedded DMA Descriptor Controller. BA

The DMA modules shown in the block diagrams implement the following functionality:• Read DMA –The Read DMA module sends memory read TLPs upstream and

Design Implementation102015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties,

entering user mode. Link training occurs after calibration. Refer to Reset Sequence for Hard IP for PCIExpress IP Core and Application Layer for a des

Frequently Asked QuestionsA2015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackThe following miscellaneous facts might be of assistance in troubleshootin

Additional InformationB2015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackRevision History for the Avalon-MM Interface with DMADate Version Changes Made

Date Version Changes Made• Removed Migration and TLP Format appendices, and added newappendix Frequently Asked Questions on page 11-1.• Updated inform

Date Version Changes Made• Added the following optimizations for the Descriptor Controller:• Optimized performance for smaller payloads such as 64-byt

• Setting up and Running Analysis and SynthesisSteps in Creating a Design for PCI ExpressBefore you beginSelect the PCIe variant that best meets your

Date Version Changes Made• Corrected Reset Controller in Arria 10 Devices figure in Reset andClocks chapter.• Corrected bit definitions for CvP Status

Contact (1)Contact Method AddressNote to Table:1. You can also contact your local Altera sales office or sales representative.Related Information• Te

Visual Cue Meaning“Subheading Title” Quotation marks indicate references to sections in adocument and titles of Quartus II Help topics. Forexample, “T

Visual Cue MeaningThe Subscribe button links to the Email Subscription Management Center page of the Altera website,where you can sign up to receive u

Getting Started with the Avalon-MM DMA22015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackYou can download this Qsys design example, ep_g3x8_avmm256_int

plan to replace the Descriptor Controller IP core with your own implementation, do not turn on theInstantiate internal descriptor controller in the pa

Figure 2-2: Arria 10 Avalon-MM DMA for PCI Express Qsys System Design4. Click Generate > Generate Testbench System.The Generation dialog box appear

Understanding the Simulation Generated FilesTable 2-2: Qsys Generation Output Files Directory Description<working_dir>/ep_g3x8_avmm256_integrat

• Various configuration accesses after the link is initialized• Setup of the DMA controller to read data from the Transaction Layer Direct BFM’s share

a. In the Family list, select Arria 10 (GX/SX/GT).b. In the Devices list, select All.c. In the Available devices list, select the appropriate device.

ContentsDatasheet... 1-1Arria 10 Avalon-MM D

Descriptor Controller Connectivity when Instantiated SeparatelyThis Qsys design example block diagram shows how to connect the external Descriptor Con

Parameter Settings32015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackSystem SettingsTable 3-1: System Settings for PCI ExpressParameter Value Descripti

Parameter Value Descriptionperformance forreceived requestsBalanced The 5 settings allow you to adjust the credit allocation tooptimize your system. T

Parameter Value Description• Minimum RX Buffer credit allocation -performance forreceived requests )—configures the minimum PCIespecification allowed

Parameter Value DescriptionEnable byteparity ports onAvalon-STInterfaceOn/Off When On, the RX and TX datapaths are parity protected.Parity is odd. Thi

Interface System SettingsTable 3-2: Interface System SettingsParameter Value DescriptionApplication Interfacewidth64-bit128-bit256-bitSpecifies the da

Parameter Value DescriptionEnable control registeraccess (CRA) Avalon-MMslave portOn/OffAllows read and write access to bridge registers from theinter

Parameter Value DescriptionEnable burst capabilitiesfor RXM BAR2 portsOn/Off When you turn on this option, the BAR2 RX Avalon-MM master is burst capab

Parameter Value DescriptionSizeN/A Qsys automatically calculates the required size afteryou connect your components.Device Identification RegistersTab

Related InformationPCI Express Base Specification 2.1 or 3.0PCI Express and PCI Capabilities ParametersThis group of parameters defines various capabi

Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates...4-5Channel Placement and fPLL and ATX PLL

Parameter Possible Values Default Value DescriptionBits are set to show timeout value ranges supported. Thefunction must implement a timeout value in

Parameter Value Default Value DescriptionNote:1. Throughout this user guide, the terms word, dword and qword have the same meaning that they havein th

Parameter Value DescriptionTable Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of thetable BAR indicator (BIR) are set to zero

Parameter Value DescriptionEndpoint L1acceptablelatencyMaximum of 1 usMaximum of 2 usMaximum of 4 usMaximum of 8 usMaximum of 16 usMaximum of 32 usNo

Physical Layout of Hard IP In Arria 10 Devices42015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackArria 10 devices include 1–4 hard IP blocks for PCI Ex

Figure 4-2: Arria 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTran

Figure 4-3: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTr

Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data RatesThe following figures illustrate the x1, x2, x4, and x8 channel and pin placements fo

Figure 4-6: Arria 10 Gen1, Gen2, and Gen3 x4 Channel and Pin PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2

Figure 4-8: Arria 10 Gen1 and Gen2 x1 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 2PMA Channel 0PMA Channel 3PMA Channel 2PM

Data Link Layer Errors ...

Figure 4-11: Gen1 and Gen2 x8 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2PMA Channel 1PMA Channe

Figure 4-13: Arria 10 Gen3 x2 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 4PMA Channel 3PMA Channel 2PMA Channe

IP Core Interfaces52015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackThis chapter describes the top-level signals of the Arria 10 Hard IP for PCI Expre

Figure 5-1: Signals When Descriptor Controller Is Embedded in the Avalon-MM Bridgetx_out0[<n> -1:0]rx_in0[<n>-1:0]Serial DataHard IP for P

Figure 5-2: Signals When DMA Descriptor Controller Is Instantiated Externallytx_out0[<n>-1:0]rx_in0[<n>-1:0]Serial DataHard IP for PCI Exp

The Read DMA Avalon-MM Master Port interface performs two functions:• Provides the descriptor table to the Descriptor Controller: This module sends me

Write DMA Avalon-MM Master PortThe Write DMA module fetches data from the Avalon-MM address space using this interface beforeissuing memory write requ

If burst mode is not enabled, the RX Master module only supports 32-bit read or write request. All otherrequests received from the PCIe link are consi

Figure 5-5: RXM Master Writes To Memory in the Avalon-MM Address SpaceAvRxmAddress_<n>_o[63:0]AvRxmWrite_<n>_oAvRxmWriteData_<n>_o[3

Signal Name Direction DescriptionTxsWaitRequest_oOutput When asserted, indicates that the Avalon-MM slave port is notready to respond to a read or wri

Datasheet12015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackArria 10 Avalon-MM DMA Interface for PCIe DatasheetAltera® Arria 10 FPGAs include a configu

Signal Name DirectionDescriptionCraByteEnable_i[3:0]Input Byte enableCraWaitRequest_oOutput Wait request to hold off additional requestsCraChipSelect_

Avalon-ST Descriptor Status Interface when Instantiated SeparatelyWhen DMA module completes the processing for one Descriptor Instruction, it returns

Bits Name Description[153:146]DMA Descriptor IDSpecifies up to 128 descriptors.[159:154]Reserved—DMA Descriptor Status Bus when Instantiated Separatel

Signal Name Direction DescriptionRdDCMRead_oOutput When asserted, indicates a read transaction.RdDCMWaitRequest_iInput When asserted, indicates that t

Table 5-14: Read Descriptor Controller Avalon-MM Master InterfaceSignal Name Direction DescriptionRdDTSAddress_i[7:0]Input Specifies the descriptor ad

Clock SignalsTable 5-16: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified und

Signal Direction Descriptionmust connect the pin_perst of each Hard IP instance to thecorresponding nPERST pin of the device. These pins have thefollo

Table 5-18: Status and Link Training SignalsSignal Direction Descriptioncfg_par_errOutput Indicates that a parity error in a TLP routed to the interna

Signal Direction Descriptionint_status[3:0]Output These signals drive legacy interrupts to the Application Layer asfollows:• int_status[0]: interrupt

Signal Direction Description• 00110: config.Linkwidthstart• 00111: Config.Linkaccept• 01000: Config.Lanenumaccept• 01001: Config.Lanenumwait• 01010: C

Table 1-1: PCI Express Data ThroughputThe following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8

Signal Direction DescriptionNote that not all simulation models assert the Transaction Layererror bit in conjunction with the Data Link Layer error bi

Signal Direction DescriptionMSIControl_o[15:0]Output Provides system software control of the MSI messages as definedin Section 6.8.1.3 Message Control

Signal Direction Descriptionhip_reconfig_writedata[15:0]Input 16-bit write model.hip_reconfig_byte_en[1:0]Input Byte enables, currently unused.ser_shi

Physical Layer Interface SignalsAltera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IPParameter Editor gen

Table 5-22: PIPE Interface SignalsIn the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulatio

Signal Direction Descriptionrxdatak0[3:0]Input Data/Control bits for the symbols of receive data. Bit 0corresponds to the lowest-order byte of rxdata,

Signal Direction Description• 5’b11010: Speed.Recovery• 5’b11011: Recovery.Equalization, Phase 0• 5’b11100: Recovery.Equalization, Phase 1• 5’b11101:

Signal Direction Descriptiontxelecidle0 Output Transmit electrical idle <n>. This signal forces the TX output toelectrical idle.tx_margin0[2:0]

Test SignalsTable 5-23: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Related InformationPIPE Interface Signals on page 5-225-28Test SignalsUG-01145_avmm_dma2015.05.14Altera CorporationIP Core InterfacesSend Feedback

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced errorreporting (AER) for high reliability applications.• Supp

Registers62015.05.14UG-01145_avmm_dmaSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 6-1: Co

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x100:0x16C Virtual Channel Capability Structure(Reserved

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x008 Class Code, Revision ID Type 0 Configuration Space

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x034 Reserved, Capabilities PTR Type 0 Configuration Spa

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x818 Advanced Error Capabilities and ControlRegisterAdva

PCI Express Capability StructuresFigure 6-2: MSI Capability Structure0x0500x0540x058Message ControlConfiguration MSI Control Status Register Field Des

Figure 6-5: PCI Express AER Extended Capability StructureByte Offset 31:24 23:16 15:8 7:00x8000x804 Uncorrectable Error Status RegisterPCI Express Enh

Altera-Defined VSEC RegistersFigure 6-7: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 6-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 6-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Feature Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVMaximumpayload size128, 256, 512,1024, 2048 bytes128, 256 b

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Bits Register Description Reset Value Access[0] Mask for the RX buffer uncorrectable ECC error. 1b’1 RWSUncorrectable Internal Error Status RegisterTa

Bits Register DescriptionResetValueAccess[1] When set, indicates a retry buffer uncorrectable ECC error.0RW1CS[0] When set, indicates a RX buffer unco

Bits Register Description Reset Value Access[5] When set, indicates a configuration error has been detected inCvP mode which is reported as correctabl

Figure 6-9: Block Diagram for External Descriptor ControllerAltera FPGAMemoryRead DMA Write DMA Hard IPfor PCIeRX MasterTX SlaveDMADescriptorControlle

1. Program the RD_DMA_LAST_PTR = 63.2. Program the RD_DMA_LAST_PTR = 127.3. Poll the status dword for read descriptor 63.4. Poll the status dword for

AddressOffsetRegister Access Description0x000CEP Read Descriptor FIFO Base(High)RW Specifies the upper 32 bits of the baseaddress of the read descript

AddressOffsetRegister Access Description0x0018RD_CONTROLRW[31:1] Reserved.[0]Done. When set, the DescriptorController writes the Done bit for eachdesc

AddressOffsetRegister Access Description0x010CEP Write Status and DescriptorFIFO Base (High)RW Specifies the upper 32 bits of the baseaddress of the w

Table 1-3: TLP Support Comparison for all Hard IP for PCI Express IP CoresThe table compares the TLP types that the four Hard IP for PCI Express IP Co

Read DMA and Write DMA Descriptor FormatRead and write descriptors are stored in separate descriptor tables. Each table can store up to 128 descrip‐to

AddressOffsetRegister NameDescription0x04WR_RC_HIGH_SRC_ADDRUpper dword of the write DMA source address.Specifies the address in the Avalon-MM domain

Figure 6-11: Descriptor Table FormatAssume the descriptor table includes 128 entries. The status table precedes a variable number ofdescriptors in mem

This is the upper 32 bits of the destination address.d. Program 0 to destination address 0xF000_0208.This is the lower 32 bits of the destination addr

Software Program for Simultaneous Read and Write DMAProgram the following steps to implement a simultaneous DMA transfer:1. Allocate Root Port memory

Control Register Access (CRA) Avalon-MM Slave PortTable 6-19: Configuration Space Register DescriptionsThe optional CRA Avalon-MM slave port provides

Byte OffsetRegister Dir Description14'h0018 cfg_sec_ctrl[15:0]O Secondary bus Control and Status register of thePCI-Express capability. This regi

Byte OffsetRegister Dir Description14'h0048 cfg_pr_lim_hi[43:32]O The upper 12 bits of the prefetchable limit registersof the Type1 Configuration

Byte OffsetRegister Dir Description14'h0064 ltssm_reg[4:0]OSpecifies the current LTSSM state. The LTSSM statemachine encoding defines the followi

Byte OffsetRegister Dir Description14'h006C lane_act_reg[3:0]O Lane Active Mode: This signal indicates the numberof lanes that configured during