Altera Arria 10 Avalon-MM DMA Instrukcja Użytkownika Strona 6
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Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8
lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and
8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX)
channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20%
overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to less
than 1%.
Units are Gigabits per second (Gbps).
Link Width
×2 ×4 ×8
PCI Express Gen1 (2.5 Gbps)
N/A N/A
16 Gbps
PCI Express Gen2 (5.0 Gbps) N/A 16 Gbps 32 Gbps
PCI Express Gen3 (8.0 Gbps) 15.75 Gbps 31.51 Gbps 63Gbps
Related Information
• PCI Express Base Specification 3.0
• AN 456: PCI Express High Performance Reference Design
• Creating a System with Qsys
Features
New features in the Quartus
®
II 15.0 software release:
• Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY
register programming with the Altera System Console.
• Added support for downstream burst read with a payload of size up to 4 KBytes, if Enable burst
capability for RXM BAR2 port is turned on in the Parameter Editor. Previous maximum downstream
read request payload size was 512 bytes.
The Arria 10 Avalon-MM DMA for PCI Express supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Native support for Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x4, Gen3 x8 for Endpoints. The variant
downtrains when plugged into a lesser link width or changes to a different maximum link rate.
• Dedicated 16 KByte receive buffer.
• Support for 128- or 256-bit Avalon-MM interface to Application Layer with embedded DMA up to
Gen3 ×8 data rate.
• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
1-2
Features
UG-01145_avmm_dma
2015.05.14
Altera Corporation
Datasheet
Send Feedback
- PCIe Solutions 1
- Contents 2
- Datasheet 5
- Link Width 6
- ×2 ×4 ×8 6
- Features 6
- Interface 7
- UG-01145_avmm_dma 10
- 2015.05.14 10
- Device Family Support 11
- Related Information 11
- Recommended Speed Grades 12
- Subscribe 14
- <install_dir>/ 14
- Parameter Value 16
- Directory Description 17
- Time TLP Type Payload 17
- TLP Header 17
- Creating a Quartus II Project 18
- Compiling the Design 19
- Parameter Settings 21
- Parameter Value Description 22
- Interface System Settings 25
- Error Reporting 30
- PCIe Address Space Settings 33
- IP Core Interfaces 42
- Reset & 44
- Lock Status 44
- RX Master Module 46
- TX Slave Module 48
- Signal Name Directio 49
- Description 49
- Bits Name Description 51
- Clock Signals 55
- Signal Direction Description 55
- MSI Interrupts for Endpoints 60
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Register Name 91
- Byte Offset 95
- Register Dir Description 95
- Arria 10 Reset and Clocks 100
- Clock Domains 103
- Name Frequency Clock Domain 104
- Error Handling 106
- Data Link Layer Errors 107
- Physical Layer Errors 107
- Error Type Description 107
- Transaction Layer Errors 108
- Status Bit Conditions 111
- Altera Corporation 112
- Send Feedback 112
- IP Core Architecture 113
- Hard IP for PCI Express 114
- Top-Level Interfaces 115
- Data Link Layer 116
- Physical Layer 118
- TX Packets 119
- Altera FPGA 121
- Qsys System 122
- Design Implementation 124
- SDC Timing Constraints 125
- Frequently Asked Questions 126
- Additional Information 127
- Date Version Changes Made 128
- How to Contact Altera 130
- Contact 130
- Contact Method Address 130
- Typographic Conventions 131
- Visual Cue Meaning 131
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