Altera Arria V GT FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 41)

Chapter 2: Board Components 2–31

General User Input/Output

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

Table 2–19 lists the LCD pin definitions, and is an excerpt from Lumex data sheet.

f For more information such as timing, character maps, interface guidelines, and other

related documentation, visit www.lumex.com.

SDI Video Output/Input

The SDI video port consists of a LMH0303SQx cable driver and a LMH0384SQ cable

equalizer. The PHY devices from National Semiconductor interface to single-ended

75- SMB connectors.

The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit

high definition (HD), and 3.0 Gbit dual-link HD modes. Control signals are allowed

for SD and HD modes selections, as well as device enable. The device can be clocked

by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to

incoming signals within 50 ppm using the UP and DN voltage control lines to the

VCXO.

Table 2–20 lists the supported output standards for the SD and HD input.

f For more information about the application circuit of the LMH0303SQx cable driver,

refer to the cable driver data sheet at www.national.com.

Table 2–19. LCD Pin Definitions and Functions

Number

Symbol

Level

Function

—

Power supply

5 V

—GND (0 V)

— For LCD drive

4RS H/L

H: Data input

L: Instruction input

5R/W H/L

H: Data read (module to MPU)

L: Data write (MPU to module)

6 E H, H to L Enable

7–14 DB0–DB7 H/L Data bus—software selectable 4-bit or 8-bit mode

Table 2–20. Supported Output Standards for SD and HD Input

SD_HD Input Supported Output Standards Rise TIme

0 SMPTE 424M, SMPTE 292M Faster

1 SMPTE 259M Slower

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 85 86

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Altera Arria V GT FPGA Development Board Instrukcja Użytkownika Strona 41