Altera Arria V GT FPGA Development Board Instrukcja Użytkownika Pobierz pdf (Strona 8)

1–4 Chapter 1: Overview

Board Component Blocks

Arria V GT FPGA Development Board December 2014 Altera Corporation

Reference Manual

■ General user I/O

■ LEDs and displays

■ Eight dual color user LEDs

■ Two-line character LCD display

■ Three configuration select LEDs

■ One configuration done LED

■ Two HSMC interface transmit/receive (TX/RX) LEDs

■ Three PCI Express LEDs

■ Five Ethernet LEDs

■ Push buttons

■ One CPU reset push button

■ One Max II CPLD EPM2210 System Controller configuration reset

push button

■ One load image push button (to program the FPGA from flash memory)

■ One image select push button (select an image to load from flash memory)

■ Three general user push buttons

■ Eight user control DIP switches

FPGA 2

The second FPGA device (FPGA 2) connects to the following components:

■ Communication ports

■ One universal HSMC expansion port (port B)

■ One FMC port

■ C2C bridge with 29 LVDS inputs and 29 LVDS outputs, and x8 transceivers

■ One serial digital interface (SDI) channel

■ One SMA 10 Gbps transceiver channel

■ One Bull's Eye 6 Gbps transceiver channel

■ One Bull’s Eye 10 Gbps transceiver channel

■ Memory

■ 1024-MB DDR3 SDRAM with a 64-bit data bus (soft controller)

■ 512-MB DDR3 SDRAM with a 32-bit data bus (hard IP controller)

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Altera Arria V GT FPGA Development Board Instrukcja Użytkownika Strona 8