Altera Arria V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 33)

Chapter 2: Board Components 2–25

Components and Interfaces

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

10/100/1000 Ethernet (HPS)

The development board supports an RJ-45 10/100/1000 base-T Ethernet using an

external Micrel KSZ9021RN PHY and the HPS EMAC function from the Altera

Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs

RGMII connection using four data lines at 250 Mbps each for a connection speed of

1Gbps.

The Micrel KSZ9021RN PHY uses 2.5-V or 3.3-V power rails. The PHY interfaces to an

RJ-45 model with internal magnetics that can be used for driving copper lines with

Ethernet traffic.

Figure 2–7 shows the RGMII interface between the HPS (MAC) and Micrel

KSZ9021RN PHY.

Table 2–17 lists the HPS Ethernet PHY interface pin assignments.

Figure 2–7. RGMII Interface between HPS (MAC) and PHY

RGMII

Mac

Single-Port RGMII

Micrel KSZ9021RN

RJ-45

Table 2–17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference (U7)

Schematic Signal Name

Arria V SoC Pin

Number

I/O Standard Description

CLK125_NDO_LED_MODE

— — Clock out 125-MHz LED mode

ENET_HPS_GTX_CLK

D19 3.3-V CMOS 125-MHz RGMII transmit clock

ENET_HPS_INTN

A18 3.3-V CMOS Management bus interrupt

ENET_HPS_LED1_LINK

— 3.3-V CMOS Receive data active LED

ENET_HPS_LED2_LINK

— 3.3-V CMOS Transmit data active LED

ENET_HPS_MDC

L18 3.3-V CMOS Management bus data clock

ENET_HPS_MDIO

J18 3.3-V CMOS Management bus data

ENET_HPS_RESETN

— 3.3-V CMOS Device reset

ENET_HPS_RSET

— 3.3-V CMOS Device interrupt

ENET_HPS_RX_CLK

G21 3.3-V CMOS RGMII receive clock

ENET_HPS_RX_DV

H19 3.3-V CMOS RGMII receive data valid

ENET_HPS_RXD0

E19 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD1

M17 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD2

G20 3.3-V CMOS RGMII receive data bus

ENET_HPS_RXD3

G19 3.3-V CMOS RGMII receive data bus

ENET_HPS_TX_EN

N18 3.3-V CMOS RGMII transmit enable

ENET_HPS_TXD0

H18 3.3-V CMOS RGMII transmit data bus

ENET_HPS_TXD1

F19 3.3-V CMOS RGMII transmit data bus

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 69 70

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