Altera Arria V SoC Development Board Instrukcja Użytkownika Pobierz pdf (Strona 56)

2–48 Chapter 2: Board Components

Memory

Arria V SoC Development Board July 2014 Altera Corporation

Reference Manual

DDR3_HPS_DQ28

G2 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ29

F2 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ30

M3 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ31

E1 1.5-V SSTL Class I Data bus

DDR3_HPS_DQS_P2

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

DDR3_HPS_DQS_N2

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

DDR3_HPS_DQS_P3

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 1

DDR3_HPS_DQS_N3

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 0

DDR3_HPS_ODT

H7 1.5-V SSTL Class I On-die termination enable

DDR3_HPS_RASN

G8 1.5-V SSTL Class I Row address select

DDR3_HPS_RESETN

E3 1.5-V SSTL Class I Reset

DDR3_HPS_WEN

J8 1.5-V SSTL Class I Write enable

DDR3_HPS_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U38)

DDR3_HPS_A0

N9 1.5-V SSTL Class I Address bus

DDR3_HPS_A1

M9 1.5-V SSTL Class I Address bus

DDR3_HPS_A2

N10 1.5-V SSTL Class I Address bus

DDR3_HPS_A3

M10 1.5-V SSTL Class I Address bus

DDR3_HPS_A4

A8 1.5-V SSTL Class I Address bus

DDR3_HPS_A5

B7 1.5-V SSTL Class I Address bus

DDR3_HPS_A6

B9 1.5-V SSTL Class I Address bus

DDR3_HPS_A7

A9 1.5-V SSTL Class I Address bus

DDR3_HPS_A8

D9 1.5-V SSTL Class I Address bus

DDR3_HPS_A9

C10 1.5-V SSTL Class I Address bus

DDR3_HPS_A10

K7 1.5-V SSTL Class I Address bus

DDR3_HPS_A11

J7 1.5-V SSTL Class I Address bus

DDR3_HPS_A12

F9 1.5-V SSTL Class I Address bus

DDR3_HPS_A13

E9 1.5-V SSTL Class I Address bus

DDR3_HPS_A14

D11 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

L7 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

C9 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

D8 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

G9 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

R8 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

A11 1.5-V SSTL Class I Differential output clock

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 51 52 53 54 55 56 57 58 59 60 61 ... 69 70

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