Altera Designing With Low-Level Primitives Instrukcja Użytkownika Pobierz pdf (Strona 27)

Altera Corporation 2–5

April 2007 Designing with Low-Level Primitives User Guide

Primitive Reference

Example 2–3 shows a Verilog HDL example of an ALT_OUTBUF primitive

instantiation.

Example 2–3. ALT_OUTBUF Primitive Instantiation, Verilog HDL

alt_outbuf my_outbuf (.i(internal_sig), .o(out)); //out must be declared as

an output pin

defparam my_outbuf.io_standard = "2.5 V";

defparam my_outbuf.slow_slew_rate = "on";

defparam my_outbuf.enable_bus_hold = "off";

defparam my_outbuf.weak_pull_up_resistor = "on";

defparam my_outbuf.termination = "series 25 ohms";

Example 2–4 shows a VHDL component declaration for an ALT_OUTBUF

primitive instantiation.

Example 2–4. ALT_OUTBUF Primitive Instantiation, VHDL

COMPONENT alt_outbuf

GENERIC(

IO_STANDARD : STRING :="NONE";

CURRENT_STRENGTH : STRING :="NONE";

SLOW_SLEW_RATE : STRING :="NONE";

LOCATION : STRING :="NONE";

ENABLE_BUS_HOLD : STRING :="NONE";

WEAK_PULL_UP_RESISTOR : STRING :="NONE";

TERMINATION : STRING :="NONE";

SLEW_RATE:INTEGER := -1

);

PORT (

i : IN STD_LOGIC;

o : OUT STD_LOGIC

);

END COMPONENT;

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Altera Designing With Low-Level Primitives Instrukcja Użytkownika Strona 27