Altera Designing With Low-Level Primitives Instrukcja Użytkownika Pobierz pdf (Strona 53)

Altera Corporation 2–31

April 2007 Designing with Low-Level Primitives User Guide

Primitive Reference

■ A CASCADE primitive cannot feed an OUTPUT pin primitive or a

■ The De Morgan’s inversion theorem implementation of cascaded

AND and OR gates requires all primitives in a cascaded chain to be

of the same type. A cascaded-AND gate cannot feed a cascaded-OR

gate, and vice-versa.

■ If you use the CASCADE primitive incorrectly, it is ignored and the

compiler issues a warning.

■ When you turn on the Auto Cascade Chains logic option, the

compiler automatically inserts CASCADE primitives during logic

synthesis. When you turn on the Ignore CASCADE Buffers logic

option, the compiler converts all CASCADE buffers to wire

primitives.

Example 2–24 shows a Verilog HDL example of a CASCADE primitive

instantiation.

Example 2–24. CASCADE Primitive Instantiation, Verilog HDL

cascade <instance_name> (.in(<input_wire>), .out(<output_wire>);

Example 2–25 shows a VHDL component declaration for a CASCADE

primitive instantiation.

Example 2–25. CASCADE Primitive Instantiation, VHDL Component Declaration

COMPONENT CASCADE

PORT (a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

LUT_INPUT

The LUT_INPUT buffer specifies the creation of a LUT function. The

LUT_INPUT buffer marks input signals for a LUT_INPUT. The logical

functionality of the LUT_INPUT and LUT_OUTPUT buffers is a simple

wire, but together they identify LUT boundaries.

To make a LUT, you must use both input and output buffers that bound

a cone of logic.

Example 2–26 shows a Verilog HDL example of a LUT_INPUT primitive

instantiation.

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Altera Designing With Low-Level Primitives Instrukcja Użytkownika Strona 53