Altera External Memory PHY Interface Instrukcja Użytkownika Pobierz pdf (Strona 63)

Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–47

Design Considerations

DDR2/DDR SDRAM Full-Rate Controller

The following section details the handshake read and handshake write function for

the DDR2/DDR SDRAM full-rate controller.

f For more information about the timing diagrams of a DDR2 SDRAM

High-Performance controller, refer to the Timing Diagrams chapter in the DDR and

DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide.

Handshake Mechanism Between Read Commands and Read Data

Figure 3–14 shows the read operation for a full-rate controller. The handshake

mechanism remains similar to that of the half-rate controller except for the following

differences:

1. 1T versus 2T addressing.

As the burst size is fixed at four on the memory interface, and also the address and

command datapath is based on 1T addressing, it takes two memory clock cycles to

retrieve the data from the memory for each read command, see Figure 3–14. The

first memory cycle is the read command and the second memory cycle is the NOP

command. Because of this arrangement, you see a NOP command between the

read commands.

2. Assertion of the chip select signal.

The chip select signal is asserted along with the read command because of the 1T

addressing.

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Altera External Memory PHY Interface Instrukcja Użytkownika Strona 63