Altera External Memory PHY Interface Instrukcja Użytkownika Pobierz pdf (Strona 73)

Chapter 4: Support for Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices 4–5

DDR2/DDR SDRAM

Table 4–1 shows the clock outputs that Arria GX, HardCopy II, Stratix II and

Stratix II GX devices use.

Table 4–1. DDR2/DDR SDRAM Clocking in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices (Part 1 of 2)

Design

Rate Clock Name

Postscale

Counter

Phase

(Degrees) Clock Rate

Clock

Network Type Notes

Half-rate phy_clk_1x

and

aux_half_rate_

clk

C0 0 Half-Rate Global The only clock that is

made available on the user

interface of the

ALTMEMPHY

megafunction. This clock

also feeds into a divider

circuit to provide the PLL

scan_clk signal (for

reconfiguration) that must

be lower than 100 MHz.

mem_clk_2x

and

aux_full_

rate_clk

C1 0 Full-Rate Global This clock is for clocking

DQS and as a reference

clock for the memory

devices.

Full rate aux_half_rate_

clk

C0 0 Half-Rate Global The only clock that is

made available on the user

interface of the

ALTMEMPHY

megafunction. This clock

also feeds into a divider

circuit to provide the PLL

scan_clk signal (for

reconfiguration) that must

be lower than 100 MHz.

phy_clk_1x (1)

and

mem_clk_2x

and

aux_full_

rate_clk

C1 0 Full-Rate Global This clock is for clocking

DQS and as a reference

clock for the memory

devices.

Half-rate

and full rate

write_clk_2x C2 –90 Full-Rate Global This clock is for clocking

the data out of the DDR

I/O (DDIO) pins in

advance of the DQS strobe

(or equivalent). As a

result, its phase leads that

of the mem_clk_2x by

90°.

1 2 ... 68 69 70 71 72 73 74 75 76 77 78 ... 82 83

Komentarze do niniejszej Instrukcji

Brak uwag

Altera External Memory PHY Interface Instrukcja Użytkownika Strona 73

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera External Memory PHY Interface