Altera FIR Compiler II MegaCore Function Instrukcja Użytkownika Pobierz pdf (Strona 38)

Figure 4-4: Multiple Channels on Multiple Wires

The sink interface to the FIR II IP core when transferring a packet of data over multiple channels on

multiple wires. The data width of each channel is 8 bits. Number of channels = 6, clock rate = 200 MHz,

and sample rate = 100 MHz

FIR Filter

xln_v

xln_0[7:0]

ast_sink_valid

ast_sink_data[23:0]

Controller

ast_sink_ready

FIR Compiler II MegaCore Function

Sink

xln_1[7:0]

xln_2[7:0]

control signals

ast_sink_eop

ast_sink_sop

ast_sink_error

sink_ready

packet error

Avalon

Streaming

Interface

Signals Check

UG-01072

2014.12.15

Multiple Channels on Multiple Wires

4-5

FIR II IP Core Functional Description

Altera Corporation

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Altera FIR Compiler II MegaCore Function Instrukcja Użytkownika Strona 38