Altera PowerPlay Early Power Estimator Instrukcja Użytkownika Pobierz pdf (Strona 19)

Altera Corporation 3–5

May 2008 PowerPlay Early Power Estimator For Arria GX FPGAs

Using the PowerPlay Early Power Estimator

Figure 3–1. PowerPlay Early Power Estimator Spreadsheet Main Section

Logic

A design is a combination of several design modules operating at

different frequencies and toggle rates. Each design module can have a

different amount of logic. For the most accurate power estimation,

partition the design into different design modules. You can partition your

design by grouping modules by clock frequency, location, hierarchy, or

entities.

Each row in the Logic section represents a separate design module. You

must enter the following parameters for each design module

■ Clock frequency (f

MAX

) in MHz

■ Number of combinational adaptive look-up tables (ALUTs)

■ Number of registers

■ Toggle percentage

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 57 58

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Altera PowerPlay Early Power Estimator Instrukcja Użytkownika Strona 19