
3–8 Altera Corporation
PowerPlay Early Power Estimator For Arria GX FPGAs May 2008
PowerPlay Early Power Estimator Inputs
Figure 3–3. 4-Bit Counter Example
Figure 3–4 shows the device PowerPlay Early Power Estimator
spreadsheet and the estimated power consumed by the logic in this
design.
Figure 3–4. Logic Section in the PowerPlay Early Power Estimator
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
PRN
CLRN
TQ
TFF
V
CC
V
CC
V
CC
V
CC
cout2
cout1
cout0
clock
cout3
OUTPUT
cout0cout0
OUTPUT
cout3cout3
OUTPUT
cout2cout2
OUTPUT
cout1cout1
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