Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Instrukcja Użytkownika Pobierz pdf (Strona 26)

2–16 Reference Manual Altera Corporation

Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006

Interfaces

General User Interfaces

To allow you to fully leverage the I/O capabilities of the Stratix II GX

device for debugging, control, and monitoring purposes, the following

general user interfaces are available on the board:

■ Debug Header

■ LEDs

■ 7-segment display

■ LCD interface

■ Push buttons

■ DIP switches

Debug Header (J1)

Board reference J1 is a simple 20-pin debug header connected to the

Stratix II GX device’s general user I/O. The form factor is a dual row

header such as a FCI 20-pin header (Samtec TSW-110-07-G-D). Table 2–10

lists the schematic signal name and the corresponding Stratix II GX

device pin number.

Table 2–10. Debug Header Pin-Out (Part 1 of 2)

Header Number Schematic Signal Name

Stratix II GX (U20)

Pin Number

1 D_HED0 AB30

2 D_HED1 AA23

3 D_HED2 AB23

4 D_HED3 AB33

5 D_HED4 AB32

6 D_HED5 AA26

7 D_HED6 AA25

8 D_HED7 AA34

9 D_HED8 AB34

10 D_HED9 AB29

11 D_HED10 AB28

12 D_HED11 AC32

13 D_HED12 AC31

14 D_HED13 AB24

15 D_HED14 AC24

16 D_HED15 AC34

17 D_HED16 AC33

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 39 40

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Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Instrukcja Użytkownika Strona 26